Boots – shoes – and leggings
Patent
1987-07-16
1989-06-13
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1200
Patent
active
048397962
ABSTRACT:
A digital memory system wherein a plurality of frames in the memory, each frame holding a page of data, may be rapidly accessed utilizing static column dynamic random access memories (SCRAMs). The SCRAM devices are configured such that a page of data is located on corresponding rows of a plurality of SCRAM devices, the corresponding rows being referred to as frames. Once a row has been activated into static column mode, successive accesses to the same row may be made very rapidly. In the presently preferred embodiments, a plurality of banks are provided, each bank being capable of holding one page of data in static column mode. In the preferred embodiments, a tag register and comparator are provided which are associated with each bank. The tag register contains a portion of the address which previously caused an access to its corresponding bank. An address is presented to all the tag registers and comparators. If a match occurs, a memory access to the bank corresponding to the matching tag register may be made while the row in the selected bank is still in static column mode.
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K. Shankar, "Wait-State Remover Improves Systems Performance", VLSI Systems Design, Nov. 1986, pp. 102-103, 110.
Arthur Ronald B.
Muhlestein Mark
Rorden Randall J.
Icon International, Inc.
Zache Raulfe B.
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