Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-12-16
2002-04-23
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S291000
Reexamination Certificate
active
06377099
ABSTRACT:
The present invention relates to a static clock pulse generator. Such a generator may be used in high speed low power controller circuits, for instance in complex very large scale integrated (VLSI) designs including digital signal processing (DSP). The clock pulse generator may advantageously be used in addressing for driver circuits of spatial light modulators and displays, for example of the pixelated matrix type in which a sequence of well-defined pulses must be supplied to circuits which sample high speed video data.
A known type of clock pulse generator is based on a shift register. The shift register comprises a cascaded chain of D-type flip-flops which respond to clock pulses to pass a single stored logic state from one flip-flop to the next in the chain. For a typical clock pulse generation application, all but one of the states of the flip-flops are initialised to a logic low (0) state whereas the remaining flip-flop is initialised to a logic high (1) state. The shift register is clocked at a known frequency and the circulating 1 state within the shift register is used to generate sequential pulses at the outputs of the flip-flops. This well-known technique is disclosed, for example, in U.S. Pat. No. 4,542,301 and U.S. Pat. No. 4,612,659. An improvement to this technique is disclosed in U.S. Pat. No. 4,785,297. In this case, the “master” and “slave” outputs of each of the flip-flops are used in conjunction with combinational logic gates, such as AND or NAND gates, to reduce the clocking speed of the shift register for a given number of output pulses.
It is also well-known to form clock pulse generating circuits from chained D-type latch circuits.
FIG. 1
of the accompanying drawings illustrates part of a typical CMOS circuit comprising latches 1 and 2. The construction and operation of such an arrangement is well-known and will not be described in detail. Consecutive latches such as 1 and 2 are transparent on opposite clock phases of a two phase clock represented by CK and CK-. The input and output of each latch are “NANDed” together in order to produce the clock pulses Nn And Np as illustrated in
FIG. 2
of the accompanying drawings.
FIG. 2
also illustrates the two phase clock waveforms, the D input to the first latch 1, the output M of the first latch 1 which is also the input of the second latch 2, and the output Q of the second latch 2.
A disadvantage of this arrangement is that the output pulses Nn and Np cannot be guaranteed to be non-overlapping., This can cause problems in certain applications, for example when the output pulses are used for sampling video data in pixel matrix display drivers.
Various techniques have been disclosed for reducing the capacitive loading of the clock line or lines so as to increase the maximum frequency of operation and reduce clock power consumption. For example, state-controlled clocking techniques have been suggested for use in clock pulse generating circuits. An example of this is disclosed in U.S. Pat. No. 4,746,915, in which the shift register is divided into several sub-registers of flip-flops or latches and another shift register operating at a lower frequency is used selectively to apply the clock signal to each sub-register.
For applications in which the requirement is for a single circulating 1 state, only those flip-flops or latches containing a 1 state or having a 1 state at their input require clocking. As shown in
FIG. 3
, for such applications, the signal generated by “ORing” the input and output of each flip-flop can be used to gate the clock signals supplied to the clock input of the flip-flop. Such an arrangement is disclosed in U.S. Pat. No. 5,128,974. However, such an arrangement requires a full flip-flop and several further transistors per stage. Also, the flip-flop outputs have to drive a relatively large load and this limits the maximum speed of operation.
The term “pass gate” as used herein is defined to mean a semiconductor arrangement having a main conduction path which can be controlled to transmit or block the passage of an input signal.
According to a first aspect of the invention, there is provided a static clock pulse generator comprising a clock input and N stages, characterised in that each ith one of the stages comprises a reset-set flip-flop having a set input for receiving a set signal from a gating circuit output of the (i−1)th stage and a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a gating circuit for passing a clock pulse from the clock input to an output of the gating circuit when the flip-flop is set, where 1<1≦(N−a).
The gating circuit may be arranged to hold the output of the gating circuit at an inactive state when the flip-flop is reset.
The reset input of the flip-flop of each ith stage may be arranged to receive the reset signal from an output of the flip-flop of the (i+2)th stage.
The reset input of the flip-flop of each ith stage may be arranged to receive the reset signal from the output of the gating circuit of the (i+1)th stage.
The output of the gating circuit of each ith stage may be connected to the set input of the flip-flop of the (i+1)th stage via a delay circuit. Each delay circuit may comprise a plurality of cascade-connected inverters.
The generator may comprise a first stage comprising a reset-set flip-flop having a set input for receiving a start pulse and a reset input for receiving a reset signal from the (1+a) th stage, and a gating circuit for passing a clock pulse from the clock input to the second stage when the flip-flop is set.
The generator may comprise an Nth stage comprising a reset-set flip-flop having a set input for receiving a set signal from the gating circuit output of the (N−1)th stage and a reset input, and a gating circuit for passing a clock pulse from the clock input to the reset inputs of the flip-flops of the Nth and (N−1)th stages.
Each ith stage may comprise a first switching arrangement for selectively causing the flip-flop set input to receive a set signal from the gating circuit of the (i+1)th stage and the flip-flop reset input to receive a reset signal from the (i−a)th stage.
The first stage may comprise a second switching arrangement for selectively causing the flip-flop set input to receive a set input signal from the gating circuit output of the second stage and the flip-flop reset input to receive a clock pulse from the gating circuit of the first stage.
The Nth stage may comprise a third switching arrangement for selectively causing the flip-flop set input to receive a start pulse and the flip-flop reset input to receive a reset signal from the (1+a)th stage.
At least some of the gating circuit outputs may constitute outputs of the generator.
At least some of the outputs of the flip-flops may constitute outputs of the generator.
The gating circuits may have inputs connected to the clock input.
Each of the gating circuits may comprise a pass gate and a holding device for holding the output of the pass gate at an inactive state when the flip-flop is reset.
Each of the pass gates may be a transmission gate comprising opposite conductivity metal-oxide-silicon field effect transistors whose source-drain paths are connected in antiparallel and whose gates are connected to direct and complementary outputs of the flip-flop.
The clock input may be a two phase input. The pass gates of consecutive stages may be connected to different clock input phases. The clock pulses passed by the pass gates of the stages may be of the same polarity.
The holding device of each stage may comprise a pull-down transistor whose control electrode is connected to a or the complementary output of the flip-flop.
The holding device of each stage may comprise a pull-up transistor whose control electrode is connected to a or the direct output of the flip-flop.
The clock input may be a single phase clock input. The clock pulses passed by the pass gates of consecutive stages may be of opposite polarity. The holding devices of the
Brownlow Michael James
Cairns Graham Andrew
Nu Ton My-Trang
Renner , Otto, Boisselle & Sklar, LLP
Sharp Kabushiki Kaisha
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