Static clock pulse generator and display

Details Static clock pulse generator and display Static clock pulse generator and display

2001-03-28

2002-04-23

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S296000

Reexamination Certificate

active

06377104

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static clock pulse generator. Such a generator may be used in high speed low power controller circuits, for instance in complex very large scale integrated (VLSI) designs including digital signal processing (DSP). The clock pulse generator may advantageously be used in addressing for driver circuits of spatial light modulators and displays, for example of the pixelated matrix type in which a sequence of well-defined pulses must be supplied to circuits which sample high speed video data.
2. Description of the Related Art
A known type of clock pulse generator is based on a shift register. The shift register comprises a cascaded chain of D-type flip-flops which respond to clock pulses to pass a single stored logic state from one flip-flop to the next in the chain, for example as disclosed in Horowitz and Hill, “The Art of Electronics”, Cambridge University Press, 2
nd
Edition, 1989. For a typical clock pulse generation application, all but one of the states of the flip-flops are initialised to a logic low (0) state whereas the remaining flip-flop is initialised to a logic high (1) state. The shift register is clocked at a known frequency and the circulating 1 state within the shift register is used to generate sequential pulses at the outputs of the flip-flops. Applications and embodiments of this well-known technique are disclosed, for example, in U.S. Pat. No. 4,542,301 and U.S. Pat. No. 4,612,659. An improvement to this technique is disclosed in U.S. Pat. No. 4,785,297. In this case, the “master” and “slave” outputs of the edge-triggered flip-flops are used in conjunction with combinational logic gates, such as AND or NAND gates, to reduce the clocking speed of the shift register for a given number of output pulses.
FIG. 1
of the accompanying drawings illustrates part of a typical CMOS circuit comprising D-type latches
1
and
2
. The construction and operation of such an arrangement is well-known and will not be described in detail. Consecutive latches such as
1
and
2
are transparent on opposite clock phases of a two phase clock represented by CK and !CK. The input and output of each latch are “NANDed” together in order to produce the clock pulses Nn and Np.
Various techniques have been disclosed for reducing the capacitive loading of the clock line or lines so as to increase the maximum frequency of operation and reduce clock power consumption. For example, state-controlled clocking techniques have been suggested for use in clock pulse generating circuits. An example of this is disclosed in U.S. Pat. No. 4,746,915, in which the shift register is divided into several sub-registers of flip-flops or latches and another shift register operating at a lower frequency is used selectively to apply the clock signal to each sub-register.
For applications in which the requirement is for a single circulating 1 state, only those flip-flops or latches containing a 1 state or having a 1 state at their input require clocking. As shown in
FIG. 2
, for such applications, the signal generated by “ORing” the input and output of each flip-flop can be used to gate the clock signals supplied to the clock input of the flip-flop. Such an arrangement is disclosed in U.S. Pat. No. 5,128,974. However, such an arrangement requires several further transistors per stage. Also, the flip-flop outputs have to drive a relatively large load and this limits the maximum speed of operation.
SUMMARY OF THE INVENTION
The term “D-type latch” as used herein refers to a circuit which has a clock input, a data input and a direct or inverted output and which operates such that, when the clock signal supplied to the clock input is active, the output suppleis a direct or inverted version of the signal at the input (the latch is “transparent”) whereas, when the clock signal is inactive, the output is held or “latched” at its current value irrespective of the state of the input signal. The term “D-type flip-flop” as used herein refers to an edge-triggered device which is generally formed of two cascaded D-type latches, possibly including additional circuitry. D-type latches and D-type flip-flops are referred to collectively herein as “D-type circuits” so that a D-type circuit may be a D-type latch or a D-type flip-flop.
According to a first aspect of the invention, there is provided a static clock pulse generator comprising a main clock input and N stages, each ith one of which comprises: a D-type circuit having a reset input for receiving a reset signal from an (i+a)th stage, where a is greater than or equal to one, and a data input; and a gating circuit having an output for supplying a pulse to the data input in response to a D-type circuit output signal of an (i−1)th stage and a clock pulse at the main clock input, where l<i≦(N−a).
Each D-type circuit may be a D-type latch.
Each of at least one of the stages may have an output for supplying the D-type circuit output signal and constituting an output of the generator.
The reset input of the D-type circuit of each ith stage may be arranged to receive the reset signal from the output of the gating circuit of the (i+a)th stage.
The reset input of the D-type circuit of each ith stage may be arranged to receive the D-type circuit output signal of the (i+a)th stage as the reset signal.
Each stage may comprise a delay circuit disposed between the gating circuit output and the D-type circuit data input of each stage. Each delay circuit may comprise a plurality of cascade-connected inverters.
Each stage may comprise 4 switching arrangement for selectively-connecting the D-type circuit reset input to receive the reset signal from the (i−a)th stage and causing the gating circuit to supply the pulse to the data input in response to the D-type circuit output signal of the (i+1)th stage and the clock pulse at the main clock input, where (1+a)≦i<N. Each switching arrangement may comprise a plurality of transmission gates.
The D-type circuit of each ith stage may comprise a clock input for receiving the D-type circuit output signal of the (i−1)th stage.
The switching arrangement may be arranged selectively to connect the D-type circuit clock input of each ith stage to receive the D-type circuit output signal of the (i+1)th stage.
The first stage may comprise: a D-type circuit having a reset input, for receiving a reset signal from a (1+a)th stage, and a data input; and a gating circuit for supplying a pulse to the D-type circuit data input in response to a start pulse and a clock pulse at the main clock input.
The switching arrangement may be arranged selectively to connect the reset signal from the first stage to the D-type circuit reset input of the first stage.
The Nth stage may comprise: a D-type circuit having a data input, an output and a reset input for receiving a reset signal from the D-type circuit output; and a gating circuit having an output for supplying a pulse to the data input in response to the D-type circuit output signal of the (N−1)th stage and a clock pulse at the main clock input.
The main clock input may comprise a complementary clock input and the gating circuits of consecutive pairs of stages may be arranged to respond to complementary clock pulses at the complementary inputs. Each gating circuit may comprise a first transistor whose common electrode is connected to the main clock input, whose output electrode forms an enabled data input of the D-type circuit and whose control electrode is responsive to the D-type circuit output signal of the preceding stage. Each gating circuit may comprise a second transistor whose common electrode is connected to a first supply line and whose output electrode is connected to the output electrode of the first transistor. The control electrode of the second transistor may be arranged to receive the D-type circuit output signal of the preceding stage.
The control electrode of the first transistor may be connected to a bias voltage source which is arrang

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