Static clock generator

Details Static clock generator Static clock generator

1995-12-15

1998-04-14

Butler, Dennis M.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting, per se, of an ac input to corresponding dc at an...

327113, G06F 108

Patent

active

057404100

ABSTRACT:
A processing system includes clock circuitry that statically multiplies/divides a stimulus signal which can then be removed while a resultant product clock is still generated, A cascaded--dual tap delay line is employed having a single phase inversion which is looped back and logically ORed with the first edge of the stimulus signal to induce oscillation. A multiplier/divisor control signal adjusts the "N" times multiplication by disabling the loop after the desired number of pulses is achieved within the period of the stimulus signal. 1/M multiplication is achieved by disabling the loop from oscillating for M stimulus clocks. Multiple frequencies can be dynamically realized on-the-fly without resynchronization by combining delayed clock pulses with a multiplexer.

REFERENCES:
patent: 4231104 (1980-10-01), St. Clair
patent: 5167024 (1992-11-01), Smith et al.
patent: 5175453 (1992-12-01), Chang et al.
patent: 5448205 (1995-09-01), Rothermel

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