Static bootstrap semiconductor drive circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307443, 307449, 307578, 307601, H03K 1706, H03K 19094

Patent

active

045544697

ABSTRACT:
A semiconductor circuit has a static bootstrap circuit, which includes a first MOS transistor with an input signal supplied to the gate and having the current path connected between a voltage source terminal and a node, a second MOS transistor having the gate connected to receive an inverted form of the input signal after a delay time and having the current path connected between the node and a reference potential terminal and a capacitor connected between the gate of the first MOS transistor and the node. The semiconductor circuit also has a short pulse generator. The bootstrap circuit further includes a third MOS transistor having the current path connected between the output terminal of the short pulse generator and the node and with the input signal supplied to the gate and fourth and fifth MOS transistors having the respective gates connected to the gates of the first and second MOS transistors and the respective current paths connected in series between the voltage source terminal and reference potential terminal.

REFERENCES:
patent: 4122361 (1978-10-01), Clemen et al.
patent: 4165541 (1979-08-01), Varshney et al.
patent: 4500799 (1985-02-01), Sud et al.
IBM Technical Disclosure Bulletin, vol. 19, No. 1, Jun. 1976, pp. 28-29, Huffman, D. R.; Rossi, F. R.; Shea, D. J. "Memory Address Decode Circuit".
Joynson et al., "Eliminating Threshold Losses in MOS Circuits by Bootstrapping Using Varactor Coupling" IEEE Journal of Solid-State Circuits, vol. SC-7, No. 3, Jun. 1972.

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