Static bistable flip-flop circuit obtained by utilizing CMOS tec

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307451, 307481, 307576, 377117, 377 79, H03K 3037, H03K 3356, H03K 1704, H03K 19017

Patent

active

047032006

ABSTRACT:
A static bistable flip-flop circuit using CMOS technology. The flip-flop reduces the number of CMOS transistors by not using two complimentary transistors in parallel for certain switches. This reduces the risk of transparency which is inherent with conventional CMOS complimentary transistors. Between the input and output of the circuit there is only a first N channel transistor, a first inverter, a second N channel transistor and a second inverter connected in series.

REFERENCES:
patent: 4250406 (1981-02-01), Alaspa
patent: 4253162 (1981-02-01), Hollingsworth
patent: 4390987 (1983-06-01), Best
patent: 4495628 (1985-01-01), Zasio
Patents Abstracts of Japan, vol. 4, No. 28 (E-1) [510], 8 mars 1980; & JP-A-55 3234 (Tokyo Shibaura Denki K.K.) 11.01.1980.
Siemens Forschungs-und Entwicklungsberichte, vol. 5, No. 6, 1976, pp. 344-349, Springer-Verlag, Berlin, DE; E. Gonauser et al.: "A Master Slice Design Concept Based on Master Cells in ESFI-SOS-CMOS Technology", p. 345, colonne de droite, lignes 2-6; p. 347, FIG. 7.

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