State sequence dependent read only memory

Details State sequence dependent read only memory State sequence dependent read only memory

1986-10-17

1987-12-29

Harkcom, Gary V.

Cryptography

Cryptanalysis

364200, 380 23, 380 25, H04L 900

Patent

active

047165863

ABSTRACT:
The addresses of firmward (ROM) being interrogated to ascertain data are continuously monitored. Selected key addresses are recognized by address detection means. Timing means is then actuated to count a preset number of address accesses, system clock cycles, or other suitable timing means. A substitute address is provided to the firmware when the timer counts down. If the incoming address is in the correct sequence then the substituted address will be the same as the incoming address and correct data will be provided by the ROM. Otherwise, incorrect data will be provided. Alternately, after countdown the incoming address can be compared with the expected incoming address. If the comparison indicates identity then the incoming address can be supplied to the firmware. Otherwise, an incorrect substitute address can be provided to the input of the firmware or incorrect substitute data can be provided on the output of the firmware. In all versions correct data will only be provided if the firmware is interrogated in the correct address sequence.

REFERENCES:
patent: 4120030 (1978-10-01), Johnstone
patent: 4306289 (1981-12-01), Lumley
patent: 4377844 (1983-03-01), Kaufman
patent: 4433211 (1984-02-01), McCalmont et al.
patent: 4471163 (1984-09-01), Donald et al.
patent: 4519036 (1985-05-01), Green
patent: 4525599 (1985-06-01), Curran et al.
patent: 4573119 (1986-02-01), Westheimer et al.

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