State retention within a data processing system

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S200000, C327S215000, C327S219000, C327S333000

Reexamination Certificate

active

07365596

ABSTRACT:
Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

REFERENCES:
patent: 5075570 (1991-12-01), Shewchuk et al.
patent: 5162667 (1992-11-01), Yasui et al.
patent: 5270581 (1993-12-01), Nakamura
patent: 6141237 (2000-10-01), Eliason et al.
patent: 6195754 (2001-02-01), Jardine et al.
patent: 6246265 (2001-06-01), Ogawa
patent: 6255862 (2001-07-01), Kumagai et al.
patent: 6291869 (2001-09-01), Ooishi
patent: 6362675 (2002-03-01), Alwais
patent: 6424196 (2002-07-01), Pomet
patent: 6433586 (2002-08-01), Ooishi
patent: 6525984 (2003-02-01), Yamagata et al.
patent: 6635934 (2003-10-01), Hidaka
patent: 6643208 (2003-11-01), Yamagata et al.
patent: 6774663 (2004-08-01), Moreaux et al.
patent: 7215188 (2007-05-01), Ramaraju et al.
patent: 2002/0159305 (2002-10-01), Yoo et al.
patent: 2003/0067322 (2003-04-01), Stan et al.
patent: 2004/0061135 (2004-04-01), Ikeno et al.
patent: 1 098 324 (2001-05-01), None
Zyuban, Victor et al.; “Low Power Integrated Scan-Retention Mechanism”; ISLPED '02; Aug. 12-14, 2002; pp. 98-102; ACM (18 page related presentation included).
Shigematsu, Satoshi et al.; “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits”; IEEE Journal of Solid-State Circuits; Jun. 1997; pp. 861-869; vol. 32, No. 6; IEEE.
Levy, Paul S. et al. “Power-Down Integrated Circuit Cuilt-In Self-Test Structures”; 1991 IEEE VLSI Test Symposium; 1991; IEEE.
Padhye, filed concurrently.
PCT application PCT/EP03/00435, Chun, filed Jan. 17, 2003.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

State retention within a data processing system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with State retention within a data processing system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and State retention within a data processing system will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2753483

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.