State retention power gating latch circuit

Details State retention power gating latch circuit State retention power gating latch circuit

2007-01-16

2007-01-16

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S208000, C327S218000

Reexamination Certificate

active

11125462

ABSTRACT:
A method of power gating a latch including detecting a state of the latch, detecting a power gate signal, providing power to the latch while the power gate signal is negated, and removing power from the latch when the power gate signal is asserted and the latch is in a predetermined state. The method may include any one or more of pulling a node of the latch to a selected state while the power gate signal is asserted to ensure that the latch powers up in the predetermined state, providing a signal indicative of the latch state and the power gate signal to respective inputs of a logic gate having an output indicative thereof, switching a supply voltage to a power input of the latch based on a state of the output of the logic gate, and closing a switch to pull a node of the latch low.

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Paul S. Levy,Power-Down Intergrated Circuit Built-In Self-Test Structures,IEEE VLSI Test Sumposium, Paper 2.1 1991, pp. 30-33.

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