State parser for a multi-stage graphics pipeline

Details State parser for a multi-stage graphics pipeline State parser for a multi-stage graphics pipeline

1998-08-04

2001-07-31

Tung, Kee M. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S519000, C345S556000, C345S559000, C345S561000

Reexamination Certificate

active

06268874

ABSTRACT:

TECHNICAL FIELD
This invention pertains to the field of graphics processing and more specifically, to process primitives in a pipeline graphics processing system.
BACKGROUND ART
Graphics processing is the most processor-intensive and memory-consuming component of the computer system. Thus, the industry is constantly searching for ways to optimize graphics processing in order to produce the high-quality images users have come to expect at an affordable price.
Data to be processed by modern graphics processors may be manipulated in many different ways, depending on resources and the desired image quality. For example, textures may be generated by processing data using a bi-linear filter which calculates a weighted average for each pixel from four texels adjacent to the point in a texture that most closely maps to the pixel. Or, the data may be processed using a tri-linear filter which uses mipmap levels just less and greater in resolution to the pixel, and also uses the four texels in each level that most closely map to the pixel. There are many different states under which data may be processed. It is often necessary to use different states to process different data even in a single refresh cycle. Some data comprising pixels or primitives intended for display on a screen may require one state and some may require a second or third state. For example, for a dithering process, a series of primitives may be processed using a first dithering algorithm, and a next series of primitives may be processed using a different dithering algorithm. Or, for filtering, a first primitive may require tri-linear filtering, but a next primitive may only need point sampling. Thus, in addition to the complicated arithmetic operations required to be performed on graphics data, the graphics processor designer must provide the capability to perform these operations in accordance with a specific state. This entails keeping track of an associated state for each primitive to be processed.
A first example of a system of tracking and applying the state of a primitive is displayed in
Figure 1
a.
In this system, the state data
108
to be applied to all primitives are stored in a register which is accessed by the processing elements
102
upon processing primitive data
104
. The primitive data
104
is transmitted through a pipeline
100
through the various processing elements
102
. This system saves on cost; however, if the state changes between a first and second primitive, the system must wait for the pipeline
100
to flush all data relating to the first primitive before applying the new state to the second primitive. This causes delays in processing and display which may be unacceptable to the user.
A second example of a system of tracking and applying the state of a primitive is displayed in
Figure 1
b.
In this system, the state data
108
is transmitted along with each primitive
104
. Thus, in this embodiment, if the state changes between two primitives
104
, the second primitive
104
can be immediately operated upon in accordance with the new state
108
. However, this configuration requires more hardware to store the state data
108
associated with each primitive
104
and is very expensive in implementation.
Thus, a system is needed for processing graphics data which can respond quickly to state changes while minimizing the use of additional hardware.
SUMMARY OF THE INVENTION
In accordance with the present invention, a parser is coupled to an incoming data stream to insert an end of state token at the end of a group of state data and an end of primitive token at the end of a group of primitive data to create a parsed data stream. The parsed state stream is transmitted to a state controller which loads state data into shadow stages. The state controller validates a shadow stage upon receiving an end of state group token which signifies that the entire group of state information has been loaded into the shadow stage. The parsed primitive data is transmitted to primitive controllers, which are coupled together serially. The primitive controllers load the data into working registers in response to receiving an end of primitive group token and verifying that the valid bit for the shadow stage has been set. The primitive is then processed in accordance with the loaded state.
In a preferred embodiment, the primitive controllers prevent primitive data from being transmitted into a processing element responsive to receiving an end of primitive_B (Begin) token. Upon receiving an end of primitive_E (End) token, the primitive controller ascertains whether the first shadow stage has been validated. If it has, the primitive controller loads the state data in the first shadow stage into the working stage, and allows the primitive data to be transmitted to the processing element, where it is processed in accordance with the state information in the working stage. Thus, state changes may be implemented on a primitive by primitive basis without unnecessary delay. In a preferred embodiment, there are multiple processing elements and primitive controllers associated with each processing element. In another preferred embodiment, there are multiple processing stages, and state controllers associated with each processing stage.
In an alternate embodiment, a dirty bit is used to indicate whether the state information received by the state controller is identical to previously received state information. When a state controller identifies that the state has changed from a first state to a second state, the state controller marks the dirty bit associated with the shadow stage having the changed state information. When the primitive controller receives an end of primitive_B token, the primitive controller ascertains whether the dirty bit of the first shadow stage associated with its processing element is marked or unmarked. If the dirty bit is unmarked, the primitive controller does not prevent the primitive data from being transmitted to the processing element and the primitive is processed without delay in accordance with the existing state information in the working registers. If the dirty bit is marked, the primitive controller prevents the primitive data from being transmitted until an end of primitive_E token is received, and the primitive controller verifies that the first shadow stage is validated indicating that the changed state information has been loaded into the registers. This embodiment provides faster processing of primitives since primitives having identical states are processed without delay. Additionally, this embodiment advantageously allows the use of a minimal amount of shadow stages, thus eliminating much of the additional hardware required to track state information. However, state information is still tracked for each primitive data, thus allowing for greater flexibility in changing states for different primitives and minimizing the latency of the pipeline.


REFERENCES:
patent: 5010515 (1991-04-01), Torborg, Jr.
patent: 5325493 (1994-06-01), Herrell et al.
patent: 5337410 (1994-08-01), Appel
patent: 5485559 (1996-01-01), Sakaibara et al.
patent: 5838383 (1998-11-01), Chimoto et al.

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