Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Patent
1995-11-08
1998-09-22
Chin, Wellington
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
375376, 327147, H03L 706
Patent
active
058119981
ABSTRACT:
A digital phase lock loop synchronizes a first signal to a second signal having a predefined frequency. The first signal usually has an instantaneous frequency greater than the predefined frequency, so that the first signal is constantly gaining phase with respect to the second signal. The digital phase lock loop performs periodic correction cycles by detecting a predefined phase relationship between the first signal and the second signal, and when the predefined phase relationship is detected, expanding the first signal in phase by a predetermined amount. Preferably, the first signal is generated by clocking a frequency divider with a clocking frequency, and the first signal is expanded in phase by inhibiting the clocking of the frequency divider for one clocking cycle for each correction cycle. Preferably, the predetermined phase relationship is detected when the second signal has a predetermined logic state coincident with clocking by the clocking signal and a predetermined state of the frequency divider. The digital phase lock loop can be used in a data processor system for synchronizing data processor clocks to a reference clock at a submultiple of the data processor clocking frequency, by obtaining each data processor clock from an initial stage of the frequency divider in a digital phase lock loop for each processor.
REFERENCES:
patent: 3789308 (1974-01-01), Lowdenslager
patent: 4441195 (1984-04-01), Baldwin et al.
patent: 4815109 (1989-03-01), Kao
patent: 4975651 (1990-12-01), Hagiwara
patent: 5012198 (1991-04-01), Okawa et al.
patent: 5036216 (1991-07-01), Hohmann et al.
patent: 5061907 (1991-10-01), Rasmussen
patent: 5068628 (1991-11-01), Ghoshal
S. Mori et al, "Performance Improvement of All Digial Phase Locked Loop With Adaptive Multilevel Quantized Phase Comparator"; The Transactions of the Institute of Electronics, Information and Comm. Engineers, vol. E72, No. 3, Mar. 1989, Tokyo, JP, pp. 194-201.
W. Rosnik, "All Digital Phase Locked Loops Using The 74HC/HCT297", Electronic Components and Applications, vol. 9, No. 2, 1989, Eindhoven, NL pp. 66-89.
Kurita et al., "PLL-Based BiCMOS On-Chip Clock Generator for Very High-Speed Microprocessor," IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, IEEE, New York, N.Y., pp. 585-589.
Miyazawa et al., "A BiCMOS PLL-Based Data Separator Circuit With High Stability and Accuracy," IEEE Journal of Solid-State Circuits, vol. 26, No. 2, Feb. 1991, IEEE, New York, N.Y., pp. 116-121.
M.G. Johnson & E.L. Hudson, "A Variable Delay Line PLL for CPU-Coprocessor Synchronization," IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, IEEE, New York, N.Y., pp. 1218-1223.
L.A. Glasser & D.W. Dobberpuhl, The Design and Analysis of VLSI Circuits, Addison-Wesley Publishing Co., Reading, Mass., 1985, pp. 360-374.
M.W. Wakayama & A.A. Abidi, A 30-MHz Low-Jitter High-Linearity CMOS Voltage-Controlled Oscillator, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, Dec. 1987, IEEE, New York, N.Y., pp. 1074-1081.
RCA Integrated Circuits, RCA Corp., Summerville, N.J., 1976, pp. 465-469.
Lundberg James R.
Wolrich Gilbert M.
Chin Wellington
Corrielus Jean B.
Digital Equipment Corporation
Fisher Arthur W.
Gupta Krishnendu
LandOfFree
State machine phase lock loop does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with State machine phase lock loop, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and State machine phase lock loop will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1625823