State machine operating in multiple parallel phase and method th

Details State machine operating in multiple parallel phase and method th State machine operating in multiple parallel phase and method th

1992-12-30

1995-02-28

Bowler, Alyssa H.

Boots, shoes, and leggings

3642295, 3642305, 36423222, 3642341, 3642389, 3642387, 3642397, 3642398, 3642408, 36424292, 36424291, 3642449, 3642473, 3642599, 3642596, 3642641, 3642647, 3642676, 364269, 364DIG1, 364DIG2, 326 40, G06F 108, G06F 124, G06F 1134, G06F 1342

Patent

active

053945573

ABSTRACT:
A state machine circuit comprising a first phased circuit clocked by a first phased clock and a second phased circuit clocked by a second phased clock. The first phased circuit includes a first input register which sequences and stores at least one input signal; a first combinatorial logic network which produces a number of output control signals wherein each of the control signals has a next state signal and a jump index signal; a first multiplexer to select one of the output control signals; and a first output register which sequences and stores the selected output control signal and also (i) feeds back the next state signal into the first combinatorial logic network, (ii) outputs the jump index into a second selector, and (iii) outputs the selected control signal, absent the next state signal and the jump index, to a device. The second phased circuit is identical in structure and function to the first phased circuit and includes a second input register, a second combinatorial logic network, a second multiplexer and a second output register.

REFERENCES:
patent: 4764126 (1988-08-01), Knight et al.
patent: 4818200 (1989-10-01), Asphar et al.
patent: 5168177 (1992-12-01), Shankar et al.
patent: 5287017 (1994-02-01), Narasimhan et al.

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