State machine design for generating empty and full flags in an a

Details State machine design for generating empty and full flags in an a State machine design for generating empty and full flags in an a

1995-12-06

1998-01-27

Treat, William M.

G06F 1200

Patent

active

057129924

ABSTRACT:
A state machine for generating a flag that represents the fullness of a FIFO buffer is disclosed. The present invention generates a set of next state variables that are derived generally from a combination of three previous state variables and three additional inputs representing an internally generated look-ahead flag, an external write clock and an external read clock. The next state variables are derived specifically from a product of the previous state variables and complement signals of the previous state variables. The full flag is generated using digital logic decoding techniques that manipulate inputs from the three next state variables, a read clock signal and a write clock signal and a look-ahead decoded internal full flag signal. An empty flag can be generated by switching the read and write clock inputs and changing the look-ahead decoded internal full flag to a look-ahead decoded internal empty flag. All of these features are realized without requiring any counters, adders or decoders in the speed path of the state machine.

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