State machine architecture partitionable into control and...

Details State machine architecture partitionable into control and... State machine architecture partitionable into control and...

2006-01-10

2006-01-10

Huynh, Kim (Department: 2182)

Electrical computers and digital processing systems: multicomput

Network-to-computer interfacing

C370S463000, C375S219000, C375S220000

Reexamination Certificate

active

06985968

ABSTRACT:
A system and method for optimizing state machine transitional performance in a high speed link (HSL) protocol stack at an application node disposed in a network. An input event decoder and a state decoder decode an input event and state-specific context information relating to a particular protocol layer involved in a layer service for a specific connection. The decoded state-specific context information is utilized for personalizing a generic state machine (GSM) logic structure in order to effectuate a layer-specific state logic package that is partitionable into a control plane and a data plane. The decoded input event is processed by the personalized state machine to generate encodable output event and next-state information. In parallel with the control plane operations, parametric tests and data operations with respect to the layer service are performed in the data plane, thereby improving state machine transitional processing in the application node.

REFERENCES:
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patent: 2001/0032069 (2001-10-01), Arweiler
patent: 2004/0078717 (2004-04-01), Allred et al.
patent: WO 200228047 (2002-04-01), None

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