State machine architecture for concurrent processing of multiple

Details State machine architecture for concurrent processing of multiple State machine architecture for concurrent processing of multiple

1995-11-01

1997-06-17

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Through a circuit switch

370518, 375373, H04J 316

Patent

active

056403984

ABSTRACT:
A plurality of data streams time-division multiplexed into a single stream are concurrently processed. State vectors characteristic of each data stream are stored in unique read-write memory locations having known addresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved. The process repeats sequentially, with the next group of three clock cycles commencing immediately after the initial clock cycle of the immediately preceding group of three clock cycles.

REFERENCES:
patent: 4520479 (1985-05-01), Grima et al.
patent: 4972407 (1990-11-01), Kawai
patent: 4974223 (1990-11-01), Ancheta et al.
patent: 5317572 (1994-05-01), Satoh

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