State coverage tool

Details State coverage tool State coverage tool

2006-11-07

2006-11-07

Jones, Hugh (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S019000, C716S030000

Reexamination Certificate

active

07133817

ABSTRACT:
A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.

REFERENCES:
patent: 6074426 (2000-06-01), Baumgartner et al.
patent: 6675138 (2004-01-01), Hollander et al.
patent: 6694497 (2004-02-01), Pavey
Liu et al.; Efficient coverage analysis metric for HDL design validation; IEEE Proc. Comp. & Digital Techniques; pp. 1-6; Jan. 2001.
Gharehbaghi et al.; Behavioral test generation for VHDL processes; IEEE Proc. 12th Int. Conf. Microelectronics; pp. 123-126; Oct. 2000.

Affiliated with

Also associated with

Rating

State coverage tool does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with State coverage tool, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and State coverage tool will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3670366