State-controlled half-parallel array walsh transform

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G06F 736

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active

055746756

ABSTRACT:
A Fast Walsh Transform (FWT) processor is disclosed, based on Good's factorization, which reduces the number of adder/subtractor units to (N/2), where N is the dimension of the FWT. The process time is equal to 2p clock cycles, where p=the 2's power of N. The clock period is determined by the delay times of the processor's internal devices (multiplexers, adder/subtractors, flip-flops), and can be minimized by using high speed complementary metal oxide semi-conductor (CMOS), or equivalent. The improvements in speed, and simplicity of implementation disclosed herein, offer performance and cost benefits in the field of digital cordless telephone technology.

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patent: 5357454 (1994-10-01), Dent
Wishner, H. D., "Designing A Special Purpose Digital Image Processor", Computer Design, vol. 11, pp. 71-76, Feb. 1972.
Geadah, Y. A., and M. J. G. Corinthios, "Natural, Dyadic And Sequency Order Algorithms And Processors For The Walsh-Hadamard Transform", IEEE Trans. Computer C-26, No. 5, pp. 435-442, May, 1977.
Chung-Kwong Yuen, "Remarks On The Ordering Of Walsh Function", IEEE Trans. Computer C-21, p. 1452, Dec. 1972.
Carl N. Smartwood, "A Hybrid Walsh Transform Computer", IEEE Trans. On Computer C-22, No. 7, Jul. 1973, pp. 669-672.
Harmuth, H. F., "Transmission Of Information By Orthogonal Functions", Cpt. 4, New York, Springer, 1969.

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