Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-11-22
2002-10-22
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06469551
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a starting circuit, and, more particularly, to a starting circuit which produces a starting signal for initializing an internal circuit in a semiconductor integrated circuit device.
FIG. 1
shows a conventional starting circuit
51
in a semiconductor integrated circuit device
100
. The starting circuit
51
receives power from a high potential power supply Vcc
1
and a low potential power supply Vss.
The starting circuit
51
comprises a voltage-dividing circuit
52
, a first stage section
53
and a waveform shaping circuit
54
. The voltage-dividing circuit
52
includes resistors R
1
and R
2
connected in series between the high potential power supply Vcc
1
and the low potential power supply Vss (0 V). The voltage-dividing circuit
52
supplies the first stage section
53
with a voltage Vn
11
generated by dividing the high potential power supply voltage Vcc
1
in accordance with the ratio of the resistance values of the resistors R
1
and R
2
.
The first stage section
53
includes a resistor R
3
and an N-channel MOS transistor (hereinafter simply referred to as an NMOS transistor) TN
1
connected in series between the high potential power supply Vcc
1
and the low potential power supply Vss. The divided voltage Vn
11
is supplied to the gate of the NMOS transistor TN
1
and the NMOS transistor TN
1
goes on or off according to the level of the divided voltage Vn
11
. When the NMOS transistor TN
1
goes off, the first stage section
53
supplies the waveform shaping circuit
54
with an H level (high potential power supply level) signal S
11
. When the NMOS transistor TN
1
goes on, the first stage section
53
supplies the waveform shaping circuit
54
with an L level (low potential power supply level) signal S
11
.
The waveform shaping circuit
54
includes a plurality (for example, two) of inverter circuits
55
and
56
connected in series. The first-stage inverter circuit
55
receives the signal S
11
from the first stage section
53
. The waveform shaping circuit
54
waveform-shapes the signal S
11
to produce a starting signal STTZ and supplies it to an internal circuit
57
.
When the level of the external power supply (high potential power supply Vcc
1
) supplied to the semiconductor integrated circuit device
100
starts rising from the off state, a current starts flowing in the resistor R
3
which forms a constant current source. At this time, the divided voltage Vn
11
from the voltage-dividing circuit
52
, as shown in
FIG. 2
, rises in proportion to the rise of the external power supply voltage Vcc
1
. Because the divided voltage Vn
11
does not exceed a threshold voltage Vthn
1
of the NMOS transistor TN
1
until time t
1
, the NMOS transistor TN
1
is maintained in the off state. Accordingly, the first stage section
53
supplies the H level signal S
11
to the waveform shaping circuit
54
and the starting signal STTZ is set at the H level. In response to a high starting signal STTZ, the internal circuit (including a flip-flop circuit and a latch circuit)
57
is initialized.
Further, when the high potential power supply Vcc
1
rises and the divided voltage Vn
11
exceeds the threshold voltage Vthn
1
of the NMOS transistor TN
1
after time t
1
, the NMOS transistor TN
1
is turned on. Consequently, the waveform shaping circuit
54
outputs a low starting signal STTZ. The initialization of the internal circuit
57
is completed in response to the trailing edge of the starting signal STTZ. Subsequently, when the high potential power supply Vcc
1
becomes stable at a normal operating voltage (at which the internal circuit
57
operates normally), the starting circuit
51
holds the starting signal STTZ at the L level. Accordingly, unless the high potential power supply Vcc
1
falls below a predetermined value again, the internal circuit
57
is not reinitialized. Thus, in the semiconductor integrated circuit device
100
, the internal circuit
57
is initialized with the starting signal STTZ of the starting circuit
51
at power-on and malfunctioning of the internal circuit
57
is prevented.
If the time t
1
at which the NMOS transistor TN
1
goes on is earlier than the time at which the initialization of the internal circuit
57
is normally completed, the internal circuit
57
(i.e., the semiconductor integrated circuit device
100
) malfunctions. Accordingly, the ratio of resistance values of the resistors R
1
and R
2
is set so that the divided voltage Vn
11
may exceed the threshold voltage Vthn
1
along with the rise of the high potential power supply voltage Vcc
1
and the time t
1
may be later than the time at which the initialization of the internal circuit
57
is normally completed.
Moreover, the threshold voltage Vthn
1
of the NMOS transistor TN
1
varies widely in a range from the maximum threshold voltage Vthn
1
max to the minimum threshold voltage Vthn
1
min due to unevenness in the chip manufacturing process. Therefore, the ratio of resistance values of the resistors R
1
and R
2
is set so that the divided voltage Vn
11
may exceed the maximum threshold voltage Vthn
1
max of the NMOS transistor TN
1
. The time at which the divided voltage Vn
11
exceeds the minimum threshold voltage Vthn
1
min of the NMOS transistor TN
1
is defined as t
2
. The ratio of values of resistance of the resistors R
1
and R
2
is set so that the time t
2
may be later than the time at which the initialization of the internal circuit
57
is normally completed.
In recent years, lower voltage power supplies have been replacing high voltage power supplies, and, as shown in
FIG. 2
, a high potential power supply Vcc
2
having a lower voltage level than the high potential power supply Vcc
1
is used as an operating power supply. However, in using the power supply Vcc
2
, the resistors R
1
and R
2
having the resistance values set for the high potential power supply Vcc
1
are not suitable. Specifically, because a divided voltage Vn
12
at which the high potential power supply voltage Vcc
2
is divided does not exceed the maximum threshold voltage Vthn
1
max, the NMOS transistor TN
1
does not go on. Accordingly, the starting signal STTZ does not fall to the L level and the initialization of the internal circuit
57
is not completed.
Therefore, the ratio of resistance values of the resistors R
1
and R
2
is changed so that a divided voltage Vn
13
of the power supply Vcc
2
may exceed the maximum threshold voltage Vthn
1
max. Accordingly, the starting circuit
11
can output the L level starting signal STTZ.
However, due to the variation in the ratio of resistance of the resistors R
1
and R
2
, the time t
3
at which the divided voltage Vn
13
exceeds the minimum threshold voltage Vthn
1
min is reached more quickly. Accordingly, before the initialization of the internal circuit
57
is normally completed, the starting signal STTZ may fall. In other words, if the time t
3
at which the starting signal STTZ falls to the L level is too quick and the initialization of the internal circuit
57
is not completed normally, a malfunction may occur in the semiconductor integrated circuit device
100
. Consequently, irrespective of how the ratio of resistance of the resistors R
1
and R
2
is set, the starting circuit
51
cannot produce the starting signal STTZ which falls at the time at which an arbitrary semiconductor integrated circuit device
100
is normally initialized.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a starting circuit which produces a starting signal will surely initialize an internal circuit of a semiconductor integrated circuit device.
In one aspect of the present invention, a starting circuit is provided that operates by receiving power from high potential and low potential power supplies. The starting circuit includes a first transistor having a threshold voltage within a predetermined range. The first transistor receives a control voltage generated from the high potential and low potential power supplies and produces a signal from the time whe
Kobayashi Isamu
Sugamoto Hiroyuki
Fujitsu Limited
Lam Tuan T.
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