Starter circuit

Details Starter circuit Starter circuit

2003-06-09

2004-12-21

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S539000, C323S313000

Reexamination Certificate

active

06833742

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a starter circuit built into a main circuit, such as a band gap reference voltage circuit, and which is in operation in startup and during the unusual operation for positively starting and re-starting the main circuit.
Up to now, a circuit the operation of which is not started regularly unless a certain signal is applied to a feedback loop of an operational amplifier in starting the circuit, such as a band gap reference voltage circuit exploiting the feedback of the operational amplifier, is in need of a starter circuit of a simplified circuit structure capable of reliably starting the main circuit.
FIG. 1
shows a circuit typical of this sort of the starter circuit.
FIG. 2
shows an instance of a band gap reference voltage circuit as typical of the main circuit started by the starter circuit shown in FIG.
1
.
A conventional starter circuit
10
u
is made up by inverters INV
1
, INV
2
a NAND gate NA
1
, a delay circuit D
101
and pMOS transistors PT
2
, PT
3
. The input sides of the inverters INV
1
, INV
2
and the delay circuit D
101
are connected to a node ND
2
, while the output side node ND
5
of the inverter INV
1
is connected to the gate of the pMOS transistor PT
3
. An output side node ND
4
of the inverter INV
2
and an output side node ND
7
of the of delay circuit D
101
are connected to an input side of the NAND gate NA
1
. An output side node ND
6
of a NAND gate NA
1
is connected to the gate of the pMOS transistor PT
2
. The drain sides of the pMOS transistors PT
2
, PT
3
are connected, as an output terminal OUT
1
and a signal terminal SN
1
, respectively, to a terminal T
n2
and to a terminal T
n3
, respectively. These terminals T
n2
and T
n3
are connected to a node n
2
, as a voltage monitor point of a band gap reference voltage circuit
20
u
, now explained, and to a node n
3
, as a common gate of transistors T
101
, T
102
and T
103
, respectively.
Referring to
FIG. 2
, the band gap reference voltage circuit
20
u
is made up by an operational amplifier OPA
1
, pMOS transistors T
101
, T
102
and T
103
and by npn transistors B
101
, B
102
and B
103
, connected in a diode configuration. The transistor T
101
, a resistor R
101
and the transistor B
101
, connected in a diode configuration, are connected in series across a supply line of a power supply voltage Vcc and a supply line of a reference voltage, herein a ground potential GND, while the transistor T
102
and the transistor B
102
, connected in a diode configuration, are connected in series across the supply line of the power supply voltage Vcc and the ground potential GND. The transistor T
103
, resistor R
102
and the transistor B
103
is connected in series across the supply line of the power supply voltage Vcc and the ground potential GND.
The gates of the transistors T
101
, T
102
and T
103
are all connected to an output terminal n
3
of the operational amplifier OPA
1
.
The operational amplifier OPA
1
has its non-inverting input terminal (+) connected to the node n
1
, as a junction across the transistor T
101
and the resistor R
101
, while having its inverting input terminal (−) connected to the node n
2
, as a junction across the transistor T
102
and the transistor B
102
. An output signal of the operational amplifier OPA
1
is coupled to the gates of the transistors T
101
, T
102
and T
103
. Thus, a feedback loop is formed by the operational amplifier OPA
1
and, by this feedback loop, the currents I
1
, I
2
and I
3
of the transistors T
101
, T
102
and T
103
are controlled so that the voltages at the nodes n
1
and n
2
are equal to each other during the regular operation, as a result of which a stable voltage V
OUT
showing no dependency on the power supply voltage Vcc nor temperature dependency is output at an output terminal T
OUT
.
The foregoing is an explanation of the operation when the band gap reference voltage circuit
20
u
performs a regular operation. However, with the band gap reference voltage circuit
20
u
by itself, that is the band gap reference voltage circuit devoid of the starter circuit
10
u
, there are cases wherein, due to variations in the voltage rise in startup, the voltage V
n1
at the node n
1
is higher than the voltage V
n2
at the node n
2
, that is V
n1
>V
n2
. In such cases, the signal voltage input to the non-inverting input terminal (+) is higher than the signal voltage input to its inverting input terminal (−), so that the operational amplifier continues to output a high-level signal, and hence the transistors T
101
, T
102
and T
103
continue to be off. In such state, the band gap reference voltage circuit
20
u
cannot operate as normally.
Thus, the voltage V
n2
at the node n
2
is compulsorily made higher than the voltage V
n1
at the node n
1
by the starter circuit
10
u
to set up a normal operating state of the band gap reference voltage circuit
20
u
, with the transistors T
101
, T
102
and T
103
being turned off in the interim. When the band gap reference voltage circuit
20
u
is in the normal operating state, the transistors T
101
, T
102
and T
103
exit from the turned-off state.
In the starter circuit
10
u
, shown in
FIG. 1
, a stand-by signal STB, which is at a high level in the stand-by (operation cessation) state and at a low level in the power supplying state, is input to the input terminal IN
1
of the starter circuit
10
u
. When the stand-by signal STB is in the high level, the output terminal ND
4
of the inverter INV
2
is in the low level, while an output terminal ND
7
of the delay circuit D
101
is at a high level in the steady operating state. Consequently, the voltage of the node ND
6
on the output side of the NAND gate NA
1
is at a high level. The pMOS transistor PT
2
is then turned off, while the drain-source current path of the pMOS transistor PT
2
in a state of high impedance. Simultaneously, the standby signal STB is at a high level, so that a node ND
5
on the output side of the inverter INV
1
is in the low level, with the pMOS transistor PT
3
being in the turned-on state. Thus, the signal terminal SN
1
is at a high level. The transistors T
101
, T
102
and T
103
of the band gap reference voltage circuit
20
u
are turned off, such that the current is supplied to the source of the output transistor T
103
, however, there is no output of the constant voltage at the output terminal T
OUT
.
When the voltage of the signal input to the input terminal IN
1
is changed from the high level to the low level, the output side node ND
5
of the inverter INV
1
goes to a high level to turn off the pMOS transistor PT
3
so that the potential of the node n
3
of the band gap reference voltage circuit
20
u
is the output voltage of the operational amplifier OPA
1
. On the other hand, the output side node ND
4
of the inverter INV
2
goes to a high level, while the output side node ND
7
of the delay circuit D
101
goes to a high level during the delay time &Dgr;td. Consequently, the potential of the output side node ND
6
of the NAND gate NA
1
goes to a low level. Thus, the pMOS transistor PT
2
is turned on so that the terminal OUT
1
goes to a high level. This forcibly pulls up the potential of the node n
2
to near the Vcc level. Since the voltage applied to the inverting input terminal (−) of the operational amplifier OPA
1
goes to a low level, the node n
3
of the output side of the operational amplifier OPA
1
goes to a low level, thus turning on the three transistors T
101
, T
102
and T
103
. After the delay time &Dgr;td, the output of the delay circuit D
101
goes to a low level, so that the output node ND
6
of the NAND gate ND
1
is at a high level and hence the pMOS transistor ND
6
is at a high level. This turns off the pMOS transistor PT
2
to isolate the starter circuit from the band gap reference voltage circuit
20
u
, to permit the band gap reference voltage circuit
20
u
to start the operation by itself.
By the above-described control in which the transistor PT
3
is turned off by the starter circu

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