Start-up circuit and voltage supply circuit using the same

Details Start-up circuit and voltage supply circuit using the same Start-up circuit and voltage supply circuit using the same

2000-06-13

2001-06-05

Berhane, Adolf Deneke (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S901000

Reexamination Certificate

active

06242898

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a start-up circuit built in a voltage supply circuit, for example, a band gap reference voltage circuit, and operating at the time of start-up of the band gap reference voltage circuit so as to make the reference voltage circuit start up more reliably and to a voltage supply circuit constituted using the same.
2. Description of the Related Art
In the past, in a band gap reference voltage circuit utilizing feedback of an operational amplifier circuit (hereinafter simply referred to as an “operational amplifier”) or other circuit which does not start operating normally until some sort of signal is given in the feedback loop of the operational amplifier at the time of start-up of the circuit, a start-up circuit which is simple in configuration and able to make the circuit start up reliably has been considered necessary.
FIG. 1
is a circuit diagram of an example of a voltage supply circuit including a start-up circuit of the related art.
As illustrated, the voltage supply circuit of this related art is constituted by a start-up circuit
10
and a band gap reference voltage circuit
20
. The start-up circuit
10
is constituted by an inverter INV
101
, a NAND gate NA
101
, and a delay circuit D
101
. Note that pMOS transistors T
104
, T
105
and an inverter INV
102
also contribute to the operation of the band gap reference voltage circuit
20
, so the circuit formed by these circuit elements is also considered as a constituent part of the start-up circuit.
When receiving a standby signal STB, the start-up circuit
10
generates signals S
1
and S
2
for making the band gap reference voltage circuit
20
operate reliably in response to the standby signal STB.
The band gap reference voltage circuit
20
is constituted by an operational amplifier OPA
1
, pMOS transistors T
101
, T
102
, and T
103
, and diode-connected npn transistors B
101
, B
102
, and B
013
.
The transistor T
101
, the resistor R
101
, and the diode-connected transistor B
101
are connected in series between the supply line of the power supply voltage V
CC
and a reference potential, for example, the supply line of the ground potential GND, the transistor T
102
and the diode-connected transistor B
102
are connected in series between the supply line of the power supply voltage V
CC
and the ground potential GND, and the transistor T
103
, the resistor R
102
, and the diode-connected transistor B
103
are connected in series between the supply line of the power supply voltage V
CC
and the ground potential GND. The transistors T
101
, T
102
, and T
103
are together connected at their gates to an output terminal of the operational amplifier OPA
1
and output currents I
1
, I
2
, and I
3
in accordance with an output signal of the operational amplifier OPA
1
.
The positive input terminal (+) of the operational amplifier OPA
1
is connected to a node n
1
between the transistor T
101
and the resistor R
101
, while the negative input terminal (−) is connected to a node n
2
between the transistor T
102
and transistor B
102
. The output signal of the operational amplifier OPA
1
is supplied to the gates of the transistors T
101
, T
102
, and T
103
. For this reason, a feedback loop is formed by the operational amplifier OPA
1
. By the control of the feedback loop, during normal operation, the currents I
1
, I
2
, and I
3
of the transistors T
101
, T
102
, and T
103
are controlled so that the voltages of the nodes n
1
and n
2
become equal.
In the standby (idle) state, the output terminal of the operational amplifier OPA
1
, that is, the node n
3
, is kept in a high impedance state. During this time, since the standby signal STB is at a high level, the output terminal of the inverter INV
102
is held at a low level and the transistor T
105
turns on, so the node n
3
is held substantially at the level of the power supply voltage V
CC
. Consequently, since the transistors T
101
, T
102
, and T
103
turn off and no DC current flows, the voltages of the nodes n
1
and n
2
are not stable. When starting operation, as the standby signal STB switches from the high level to the low level, the output terminal of the inverter INV
102
switches from the low level to the high level, so the transistor T
105
turns off and the operational amplifier OPA
1
controls the voltage of the node n
3
in accordance with the input voltages of the nodes n
1
and n
2
. Accordingly, the currents I
1
, I
2
, and I
3
of the transistors T
101
, T
102
, and T
103
are controlled.
If there were no start-up circuit and the voltage of the node n
1
were higher than the voltage of the node n
2
, that is, V
n1
>V
n2
, the operational amplifier OPA
1
would continuously output a signal of the high level since the voltage input to the positive input terminal (+) is higher than the voltage supplied to the negative input terminal (−). In such a situation, the band gap reference voltage circuit
20
cannot operate normally.
As described above, the standby signal STB is held at the high level when the voltage supply circuit is idling and is switched from the high level to the low level when the voltage supply circuit starts operating. Accordingly, the illustrated start-up circuit
10
outputs a signal S
1
at a low level from the trailing edge of the standby signal STB during the delay time &Dgr;td of the delay circuit D
101
. At other times, the standby signal STB is held at the high level.
While the signal S
1
is at the low level, the transistor T
104
is on, so the current flowing through the transistor T
104
is input to the node n
2
. The emitter area of the diode-connected transistor B
101
is made larger than the emitter area of the transistor B
102
. For this reason, when the same currents flow through these transistors or a current only flows through the transistor B
102
, the voltage V
n2
of the node n
2
always becomes higher than the voltage V
n1
of the node n
1
at the beginning of the operation. As a result, in the operational amplifier OPA
1
, the voltage input to the negative input terminal (−) is higher than that input to the positive input terminal (+) and the output signal is held at the low level. According to this, the transistors T
101
, T
102
, and T
103
turn on, and the currents I
1
, I
2
, and I
3
are output.
The signal S
1
input to the gate of the transistor T
104
is held at the low level for exactly the time set by the delay time &Dgr;td of the delay circuit D
101
, then is switched to the high level. Since the transistor T
104
is on for exactly the period when the signal S
1
is at the low level and then turns off, the band gap reference voltage circuit
20
is controlled by the feedback loop formed by the operational amplifier OPA
1
, and a stable voltage V
OUT
is output from the output terminal T
OUT
free from any dependency on the power supply voltage V
CC
and temperature.
Summarizing the problem to be solved by the invention, in the voltage supply circuit of the related art described above, due to the control by the start-up circuit
10
after start-up so as to turn off the transistor T
105
and to turn on the transistor T
104
for exactly a certain constant time and then turn it off, normal start-up becomes possible regardless of the voltages of the node n
1
and n
2
while idle. Here, if the transistor T
014
is held in the on state, since the feedback loop formed by the operational amplifier OPA
1
cannot operate normally and the operational amplifier OPA
1
cannot control the transistors T
101
, T
102
, and T
103
, the control signal S
1
for controlling the on time of the transistor T
104
is generated according to the delay time of the delay circuit D
101
.
However, since the timing of the switching of the level of the signal S
1
is set by experience rather than after confirming the operational state of the band gap reference voltage circuit
20
, it is not always set to the optimum value. If the switching time is too long, the start-up time of the voltage supply circuit becomes unn

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