Start of packet receive interrupt for ethernet controller

Details Start of packet receive interrupt for ethernet controller Start of packet receive interrupt for ethernet controller

1995-05-09

1996-07-02

Eng, David Y.

Boots, shoes, and leggings

3642391, 3642840, 3642841, 3642844, G06F 1300, G06F 15173

Patent

active

055332030

ABSTRACT:
A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction with the controller the system provides for the receipt and transfer of data packets from the ethernet controller during the latency period of the network. In so doing, the overall performance of the network is enhanced.

REFERENCES:
patent: 4032899 (1977-06-01), Jenny
patent: 4075691 (1978-02-01), Davis
patent: 4493021 (1985-01-01), Agrawal
patent: 5105382 (1992-04-01), Ogasawara
patent: 5163132 (1992-11-01), DuLac
patent: 5339439 (1994-08-01), Latimer

Affiliated with

Also associated with

Rating

Start of packet receive interrupt for ethernet controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Start of packet receive interrupt for ethernet controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Start of packet receive interrupt for ethernet controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1514882