Standby system for a frequency synthesizer

Details Standby system for a frequency synthesizer Standby system for a frequency synthesizer

1990-12-26

1991-12-24

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 11, 331 25, H03L 700

Patent

active

050756389

ABSTRACT:
A synthesizer is placed in standby mode when a standby portion of a control register is set. Once standby is activated, any detectors and counters are inhibited. The inputs and outputs are reconfigured so as to minimize current drain and to stabilize the VCO control voltage. Recovery from standby is accomplished in two phases. The first phase is started by the receipt of a terminate standby signal. This enables the inputs and starts the counters. The second phase is activated when a signal is received from a feedback counter indicating it has completed a cycle. This causes the preset data to be loaded into the reference counter. The counters are then synchronized; the detector is initialized; and the detector output is enabled. The device also controls an output lock detector and reference frequency signal during the standby mode. The system is also compatible with variable modulus prescalers.

REFERENCES:
patent: 4030045 (1977-06-01), Clark
patent: 4951005 (1990-08-01), Babin et al.
patent: 4968950 (1990-11-01), Babin et al.
Seimens Data Sheet TBB 200 PLL Frequency Synthesizer.

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