Standardized digital logic chip

Details Standardized digital logic chip Standardized digital logic chip

1977-11-07

1979-07-17

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307207, 357 40, 357 41, 357 45, 357 42, H01L 2704

Patent

active

041616626

ABSTRACT:
A standardized large scale integrated (LSI) array of standard logic cells on a single complementary metal oxide semiconductor (CMOS) chip. The pattern chosen for the layout of the standard logic cells provides very high cell density and, in combination with the "roadways" provided for power and data interconnects and the availability of "cross unders" within any cell chosen, very high utility ratios of the available cells. The standardized logic chip may be used to implement a large variety of logic circuit designs by the simple expedient of a single custom mask design for the metallization pattern for each unique use.

REFERENCES:
patent: 3312871 (1967-04-01), Seki et al.
patent: 3365707 (1968-01-01), Mayhew
patent: 3638202 (1972-01-01), Schroeder
Hibberd, Integrated Circuits, McGraw-Hill, 1969, pp. 133-140.

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