Standard cells with flip-flops located in a single region and ha

Details Standard cells with flip-flops located in a single region and ha Standard cells with flip-flops located in a single region and ha

1989-07-17

1991-07-02

Hudspeth, David

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307465, 307480, 364491, H03K 19177

Patent

active

050292790

ABSTRACT:
Standard cells in which the accurate estimation of the clock routing length and the minimization of the clock routing are possible so that an optimal protection against the malfunctions due to the racing can be schemed. The standard cells includes flip-flop circuits collectively arranged in a region of the substrate; and clock routing for the flip-flop circuits with connections connecting the clock routing and each of the flip-flop circuits at shortest distance.

REFERENCES:
patent: 4694403 (1987-09-01), Nomura
patent: 4750027 (1988-06-01), Asami
patent: 4851717 (1989-07-01), Yabe
patent: 4870300 (1989-09-01), Nakaya et al.
patent: 4883980 (1989-11-01), Movimoto et al.
Van Dyke, "Physical Partitioning of Logical Functions in VLSI Chip Design" IBM T.D.B., vol. 27, No. 8, 1-1985, pp. 4648-4651.

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