Standard cells interconnection structure including a modified st

Details Standard cells interconnection structure including a modified st Standard cells interconnection structure including a modified st

1994-05-13

1995-11-21

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257207, 257211, H01L 23522, H01L 23528, H01L 23538

Patent

active

054689775

ABSTRACT:
A semiconductor integrated circuit device designed with CAD is formed of a plurality of standard cells including at least four I/O terminals. Each standard cell includes a metal interconnection for a power supply and a metal interconnection for the ground, and also includes an active element formation region and a metal interconnection layer isolated from respective interconnection layers and coupled to a plurality of I/O terminals at a position above it. If it is desired to use the metal interconnection as a power signal line, a via hole is formed in an insulator film, and the metal interconnection layer and the metal interconnection for the power supply are coupled together therethrough.

REFERENCES:
patent: 4989062 (1991-01-01), Takahashi et al.
patent: 5060045 (1991-10-01), Owada et al.
patent: 5151772 (1992-09-01), Takahashi et al.

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