Standard-cell type semiconductor logic LSI with logical amplitud

Details Standard-cell type semiconductor logic LSI with logical amplitud Standard-cell type semiconductor logic LSI with logical amplitud

1990-05-29

1993-07-06

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307448, H03K 19173, H03K 190175

Patent

active

052257185

ABSTRACT:
A standard cell type gallium arsenide logic integrated circuit device includes arrays of standard cells connected to each other on a chip substrate. Each of the standard cells includes a plurality of gallium arsenide logic gates of previously selected type such as NOR gates and an inverter. The logic gate has a direct-coupled type FET logic circuit structure. In each of the standard cells, level-shift circuits are provided only for inputs of those logic gates which are directly connected to connection terminals directly associated with the other standard cell. The level-shift circuits enhance the swing width of a logic signal transmitted between the standard cells which are associated with one another, thereby increasing the operation margin. Such a level-shift circuit is not provided for internal interconnection wirings between the logic gates inside the standard cell.

REFERENCES:
patent: 4527079 (1985-07-01), Thompson
patent: 4798978 (1989-01-01), Lee et al.
patent: 4831284 (1989-05-01), Anderson et al.
patent: 4931670 (1990-06-01), Ting
patent: 4945258 (1990-07-01), Picard et al.
patent: 4965863 (1990-10-01), Cray

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