Standard cell array having fake gate for isolating devices from

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357 42, 357 65, H01L 2702

Patent

active

048518921

ABSTRACT:
A standard cell array is disclosed having improved device isolation, customized metal routing under power busses, a gate array core cell having improved internal routing channels, and shared power busses. A fake gate is located adjacent a source of drain of a transistor within each cell, and is coupled to a supply voltage for isolating the transistors within each cell. Additional metallization strips partially overlap and extend between adjacent rows and columns, respectively, of the core cells for providing supply voltages thereto. Further metallization strips for conducting signals overlie the internal portion of the core cell and extend the entire length of the row or column of core cells.

REFERENCES:
patent: 4356504 (1982-10-01), Tozun
patent: 4570176 (1986-02-01), Kolwicz

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