Standard cell and semiconductor device including the same

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections

Reexamination Certificate

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Details

C257S207000, C257S209000, C257SE27060

Reexamination Certificate

active

07859023

ABSTRACT:
This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

REFERENCES:
patent: 6812574 (2004-11-01), Tomita et al.
patent: 2002/0063335 (2002-05-01), Ozawa et al.
patent: 2003/0039897 (2003-02-01), Morita
patent: 09-120993 (1997-05-01), None
patent: 2006-235080 (2006-09-01), None
Kotani et al. “New Design and OPC Flow for Manufacturability for 45 nm Node and Beyond”, VLSI Symposium, 2005.

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