Stalling CPU pipeline to prevent corruption in trace while...

Details Stalling CPU pipeline to prevent corruption in trace while... Stalling CPU pipeline to prevent corruption in trace while...

2006-08-29

2006-08-29

Jones, Hugh (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Emulation

C703S023000, C703S026000, C703S027000, C703S016000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07099817

ABSTRACT:
A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.

REFERENCES:
patent: 5970241 (1999-10-01), Deao et al.
patent: 6243836 (2001-06-01), Whalen
patent: 6321290 (2001-11-01), Yamashita
patent: 2003/0229823 (2003-12-01), Swaine et al.
patent: 2004/0102950 (2004-05-01), Agarwala et al.
Wong, William, MIPS On-Chip Debug Hardware, Electronic Design, Oct. 1, 2001.

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