Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-02-26
2003-03-25
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185190, C365S185220
Reexamination Certificate
active
06538923
ABSTRACT:
BACKGROUND
1. Field of Invention
The present invention relates generally to the field of electronic data storage devices. More particularly, the present invention relates to non-volatile multi-level-cell semiconductor memory devices and a method for reducing program-verify time in non-volatile multi-level-cell semiconductor memory devices.
2. Description of Related Art
Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory fabricated from semiconductors. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storage—non-volatile medium—so that the data and computer programs remain when power is removed.
Conventional semiconductor memory devices store bits of information in memory cells. The typical memory cell comprises an access transistor and a storage element such as a capacitor. Data is represented in binary notation with a “1” or a “0,” depending on the charge stored at the location. Such devices, however, require constant ambient power in order to retain the charge. Therefore, the data stored in such memory devices are susceptible to power loss.
Semiconductor memory devices that do not require ambient power to retain the data stored therein have been developed. These devices have been termed “non-volatile” semiconductor memory devices. In common designs for non-volatile semiconductor memory devices, data is internally organized in an array of sectors, each comprising a plurality of memory cells. Each sector is partitioned into segments termed a page, each page partitioned into segments termed a word, and each word partitioned into memory cells. Data is accessed for reading and programming by page, while the entire sector is accessed for erasing.
A few examples of non-volatile semiconductor memory devices include Read Only Memory (ROM), Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM). While conventional EPROM's provide reliable non-volatile storage, they typically may not be able to be reprogrammed in a practical matter. For example, EPROM's typically require exposure to Ultraviolet light to erase. This often requires that the device be removed from its host to be erased. In many applications, removing the memory is not practical to reprogram.
An Electrically Erasable Programmable Read Only Memory (EEPROM) is a type of EPROM. An EEPROM is similar to an EPROM, but can be electrically reprogrammed with voltage pulses and without special hardware. An EEPROM has the disadvantages of being expensive and having a relatively limited life span, according to the number of erased and write operations.
Another type memory having similar properties to of non-volatile memory devices is the Static Random Access Memory (SRAM). The SRAM offers high operating speeds but only maintains its ability to retain the information stored therein while power is supplied to it. Therefore, to retain its non-volatility properties, it requires constant power from a battery or other similar energy storage device. This necessitates additional hardware to maintain power to the SRAM, which increases manufacturing cost and complexity. Further, the additional hardware may put undesirable constraints on the physical size of the design.
Flash memory (or Flash RAM) is another form of non-volatile memory devices. Flash Memory devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. In addition, Flash Memory has the additional ability of electrically selectively erasing all memory cells. One characteristic of flash memory is that individual memory cells must be erased before they can be reprogrammed. Using Flash Memory devices in circuitry permits in-circuit erasing and reprogramming of the device without having to remove the memory device. The bits in a flash memory device can be modified millions of times during the lifetime of the device. Conventional flash memory devices store a single bit of data per memory cell. Each memory cell is characterized by a threshold voltage (V
t
). Within conventional flash memory devices, two possible threshold voltages (V
t
) exist.
FIGS. 1 and 1
a
show an example of a typical configuration for a conventional flash memory cell
100
in a flash memory device. A Conventional flash memory cell
100
uses a memory cell transistor
101
having a substrate
104
, a source
105
, a drain
106
, a gate
107
, and a floating gate
102
structure. A thin insulating film
103
may also be located between the floating gate
102
and the substrate
104
. Data in the flash memory device are programmed or erased by accumulation or evacuation of charge a floating gate
102
. Programming of the memory cell
100
occurs by applying a sufficient voltage difference to the transistor to cause excess electrons to accumulate on the floating gate
102
. The accumulation of the additional electrons on the floating gate
102
raises the charge on the gate and the transistor's V
t
. The transistor's V
t
is raised sufficiently above that of the applied voltage during read cycles V
r
so that the transistor does not conduct during the read cycles. Therefore, a programmed memory cell
100
will not carry current, representing the logical value “0.”
The erasure of data in a memory cell
100
is caused by a process by which a sufficient voltage difference is applied to the memory cell transistor
101
to cause the excess electrons on the floating gate
102
in the memory cell transistor
101
to evacuate the floating gate
102
. Thereby the transistor's V
t
is lowered below that of the voltage potential applied to the transistor to read data V
r
. In the erased state, current can flow through the transistor. When V
r
is applied, the current will flow through the transistor of the memory cell
100
, representing a logical value “1” stored in the memory cell
100
. The granularity by which a flash memory device can be programmed or erased may vary. Granularities down to the bit level programming/erasure are contemplated.
An example of a typical configuration for an integrated circuit including a flash memory array
200
and circuitry enabling programming, erasing, and reading for memory cells in the array
200
is shown in FIG.
2
. The flash memory array
200
includes individual cells
202
. Each cell
202
has a drain connected to a bitline
204
; each bitline
204
is connected to a bitline pull up circuit
206
and column decoder
208
. The sources of the array cells are connected to V
ss
, while their gates are each connected by a word-line
209
to a row decoder
210
.
The row decoder
210
receives voltage signals from a power supply
212
and distributes the particular voltage signals to the word-lines as controlled by a row address received from a processor or state machine
214
. Likewise, the bitline pull up circuit
206
receives voltage signals from the power supply
212
and distributes the particular voltage signals to the bitlines as controlled by a signal from the processor
214
. Voltages provided by the power supply
212
are provided as controlled by signals received from processor
214
.
The column decoder
208
provides signals from particular bitlines
204
to sense amplifiers or comparators
216
as controlled by a column address signal received from processor
214
. The sense amplifiers
216
further receive voltage reference signals from reference circuit
218
. The outputs from sense amplifiers
216
are then provided through data latches or buffers
220
to processor
214
.
Programming of the flash memory array
200
is executed on a word-line basis. The word-line
209
is considered the row address. The word-line will cross multiple bit-lines
204
. The bit-line
204
is considered the column address. Each bit-line
204
contains buffer l
Advanced Micro Devices , Inc.
Phan Trong
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