Staggered row line firing in single ras cycle

Details Staggered row line firing in single ras cycle Staggered row line firing in single ras cycle

1996-11-04

1997-11-25

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365194, G11C 800, G11C 700

Patent

active

056919514

ABSTRACT:
A row decoder circuit operates in a memory integrated circuit, such as a dynamic random access memory (DRAM), having an array of memory cells including row and columns. An address decode tree circuit receives address signals and provides decode signals being activated based on the state of the address signals. Row line driver circuits receive corresponding ones of the decode signals and an enable signal. Each row line driver circuit fires a corresponding row line when the enable signal is activated and the corresponding one of the decode signals is activated. Delay circuitry delays certain of the address signals to stagger the activation of certain of the decode signals to permit multiple row lines to fire in a single row address strobe (RAS) cycle.

REFERENCES:
patent: 4885720 (1989-12-01), Miller et al.
patent: 5274591 (1993-12-01), Waller et al.
patent: 5291443 (1994-03-01), Lim
patent: 5297087 (1994-03-01), Porter
patent: 5381368 (1995-01-01), Morgan et al.
patent: 5440517 (1995-08-01), Morgan et al.
patent: 5625790 (1997-04-01), Cutter

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