Staggered refresh for dram array

Details Staggered refresh for dram array Staggered refresh for dram array

1987-12-15

1989-12-12

Fears, Terrell W.

Electricity: electrical systems and devices

Discharging or preventing accumulation of electric charge

Specific conduction means or dissipator

36523001, 36523003, 36523005, 36518904, G11C 1300, G11C 1140

Patent

active

048872407

ABSTRACT:
According to the present invention, each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. Thus, the time required to refresh one row in each DRAM of each bank at 10 MHz, for example, is equal to 0.7 .mu.sec., or 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique avoids large power supply current spikes while minimizing the effect on memory access bandwidth.

REFERENCES:
patent: 4249247 (1981-02-01), Patel
patent: 4639858 (1987-01-01), Murray, Jr. et al.
patent: 4701843 (1987-10-01), Cohen
patent: 4754425 (1988-01-01), Bhadriraju
patent: 4796232 (1989-01-01), House

Affiliated with

Also associated with

Rating

Staggered refresh for dram array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Staggered refresh for dram array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Staggered refresh for dram array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2126552