Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
Reexamination Certificate
2005-09-30
2008-11-25
Tsai, Henry (Department: 2184)
Electrical computers and digital processing systems: processing
Processing architecture
Vector processor
C712S003000, C712S007000, C712S020000, C712S032000, C712S215000
Reexamination Certificate
active
07457938
ABSTRACT:
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and executing the operation on high order portions of the first and second source operands using a second execution stack of the processor, where the operation in the second execution stack is staggered by one or more cycles from the operation in the first execution stack. Other embodiments are described and claimed.
REFERENCES:
patent: 5073970 (1991-12-01), Aoyama et al.
patent: 5423051 (1995-06-01), Fuller et al.
patent: 5530881 (1996-06-01), Inagami et al.
patent: 5951670 (1999-09-01), Glew et al.
patent: 5978900 (1999-11-01), Liu et al.
patent: 6233671 (2001-05-01), Abdallah et al.
patent: 6505293 (2003-01-01), Jourdan et al.
patent: 6516406 (2003-02-01), Peleg et al.
patent: 6553483 (2003-04-01), Jourdan et al.
patent: 6591359 (2003-07-01), Hass et al.
patent: 6625723 (2003-09-01), Jourday et al.
patent: 6694426 (2004-02-01), Roussel et al.
patent: 6839828 (2005-01-01), Gschwind et al.
patent: 2004/0064681 (2004-04-01), Jourdan et al.
patent: 2005/0125636 (2005-06-01), Ford et al.
Hennessy et al. Computer Architecture, p. G-10, lines 12-22.
Hinton, et al., “The Microarchitecture of the Pentium® 4 Processor”. Intel Technology Journal Q1, 2001.
Espasa, et al. “Tarantula: A Vector Extension to the Alpha Architecture”. ACM Sigarch Computer Architecture News, vol. 30, Issue 2 (May 2002). pp. 281-292. (2002).
Fetterman Michael
Hammarlund Per
Hinton Glenn
Jourdan Stephan
Singhal Ronak
Intel Corporation
Trop Pruner & Hu P.C.
Tsai Henry
Tseng Cheng-Yuan
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