Stacking three dimensional leadless multi-chip module and method

Details Stacking three dimensional leadless multi-chip module and method Stacking three dimensional leadless multi-chip module and method

1992-05-26

1993-09-21

Tolin, Gerald P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

174252, 361744, 361749, H05K 720

Patent

active

052474232

ABSTRACT:
A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

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"Large Capacity Memory Board Using Stacked Chip Assembly," by Kenzo Hatada et al., The Third Microelectronics Symposium (MES '89), Jul. 1989.
"Stacked High-Density Multichip Module," by R. A. Jarvela et al., IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972, pp. 2896-2897.

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