Stacking semiconductor devices, particularly memory chips

Details Stacking semiconductor devices, particularly memory chips Stacking semiconductor devices, particularly memory chips

1997-05-27

1999-12-07

Jones, Deborah

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

257730, 257731, 257777, 257778, 257786, 257686, 257668, 257691, 257698, 257724, 361735, H01L 2302, H05K 700

Patent

active

059988649

ABSTRACT:
High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate, such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes. The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., a nickel plating).

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patent: 5212406 (1993-05-01), Reele et al.
patent: 5373189 (1994-12-01), Massit et al.
patent: 5473196 (1995-12-01), De Givry
patent: 5600183 (1997-02-01), Gates, Jr.
patent: 5614766 (1997-03-01), Takasu et al.
patent: 5656856 (1997-08-01), Kweon

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