Stacking apparatus and method for stacking integrated...

Semiconductor device manufacturing: process – Including control responsive to sensed condition – Interconnecting plural devices on semiconductor substrate

Reexamination Certificate

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C257S777000, C257SE21509, C438S015000, C228S103000

Reexamination Certificate

active

11481250

ABSTRACT:
A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

REFERENCES:
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 5270261 (1993-12-01), Bertin et al.
patent: 2002/0074630 (2002-06-01), Ando et al.
patent: A-07-014982 (1995-01-01), None
patent: A-2000-294724 (2000-10-01), None
patent: A-2001-210783 (2001-08-01), None
patent: A-2001-298146 (2001-10-01), None
patent: A-2002-151642 (2002-05-01), None
patent: A-2005-026346 (2005-01-01), None

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