Stacked type semiconductor device

Details Stacked type semiconductor device Stacked type semiconductor device

2003-09-30

2004-11-02

Clark, S. V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000

Reexamination Certificate

active

06812557

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-286515, filed Sep. 30, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stacked type semiconductor device having a plurality of stacked semiconductor integrated circuit chips.
2. Description of the Related Art
In response to demands for a reduction in the size of electronic equipment, a stacked type semiconductor device (multichip device) has been proposed which has a plurality of stacked semiconductor integrated circuit chips (LSI chips).
It is contemplated that if a stacked type semiconductor device is manufactured, chips may be individually subjected to operation tests so that only normal chips can be sorted out and stacked. However, testing the individual chips increases the time and effort required for the tests. This may create problems such as an increase in costs and a delay in delivery.
To solve these problems, it is contemplated that instead of being individually tested, the chips may be stacked before the whole module is tested. However, if any one of the stacked chips is defective, the whole module becomes defective. Consequently, yield may decrease, which increases the costs. Further, every chip may be provided with a redundancy circuit. However, since each chip is provided with the extra circuit, the costs also increase.
Therefore, it has hitherto been difficult to obtain a stacked type semiconductor device which enables stacked chips to be tested and which can prevent a decrease of yield and an increase of extra circuit.
As a prior art technique, Japanese Patent No. 2760188 discloses a technique by which one chip has a plurality of functional blocks so that a defective block can be replaced with another chip. Specifically, chips are produced beforehand each of which has a mirror symmetrical relationship with a corresponding functional block. Then, on a defective functional block, the corresponding mirror symmetrical chip is stacked. However, the mirror symmetrical chips must be tested before being stacked. This may increase the required time and effort. Further, the mirror symmetrical chip must be produced for every functional block. This may also increase the required time and effort.
Jpn. Pat. Appln. KOKAI Publication No. 2000-349229 discloses a technique of constructing a stacked type DRAM by combining defective chips (partial chips) for which part of an address space does not function correctly. However, this technique requires the chips to be tested before stacking in order to check whether or not they are defective. This may increase the required time and effort.
Jpn. Pat. Appln. KOKAI Publication No. 5-283606 discloses a semiconductor device having a plurality of stacked DRAM chips each of which is provided with a redundancy circuit. However, since every chip is provided with the redundancy circuit, this technique is very wasteful. As a result, the costs may increase.
In this manner, although the stacked type semiconductor devices have been proposed each of which has a plurality of stacked semiconductor integrated circuit chips, it has hitherto been difficult to obtain a stacked type semiconductor device which enables stacked chips to be tested and which can prevent a decrease of yield and an increase of extra circuit.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a stacked type semiconductor device comprising a predetermined semiconductor integrated circuit chip and at least one semiconductor integrated circuit chip which are stacked, the at least one semiconductor integrated circuit chip including a group of circuit blocks, and the predetermined semiconductor integrated circuit chip comprising a storage section configured to store defect information indicative of a defective circuit block if the group includes the defective circuit block and a replacement circuit section configured to replace the defective circuit block.


REFERENCES:
patent: 4021838 (1977-05-01), Warwick
patent: 4721995 (1988-01-01), Tanizawa
patent: 4954875 (1990-09-01), Clements
patent: 5426072 (1995-06-01), Finnila
patent: 5936302 (1999-08-01), Pedersen et al.
patent: 6353264 (2002-03-01), Coronel et al.
patent: 6486528 (2002-11-01), Pedersen et al.
patent: 6614106 (2003-09-01), Matsuo et al.
patent: 6624506 (2003-09-01), Sasaki et al.
patent: 6670701 (2003-12-01), Matsuura et al.
patent: 6737738 (2004-05-01), Koh et al.
patent: 05-283606 (1993-10-01), None
patent: 2760188 (1998-03-01), None
patent: 2000-349229 (2000-12-01), None
patent: 2001-102479 (2001-04-01), None
patent: 2002-110865 (2002-04-01), None

Affiliated with

Also associated with

Rating

Stacked type semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked type semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked type semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3326459