Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-04-16
2002-06-04
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S723000, C257S777000, C438S107000, C438S109000
Reexamination Certificate
active
06400007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The invention relates to a stacked semiconductor package structure having films and method for manufacturing the films, in particular, to a semiconductor package structure capable of preventing the semiconductor chips from being badly electrically connected or short-circuited and facilitating the manufacturing processes.
2. Description of the Related Art
To meet the demands of manufacturing small, thin, and light products, a lot of semiconductor chips can be stacked. However, when stacking a lot of semiconductor chips, the upper semiconductor chip will contact and press the wirings of the lower semiconductor chip. In this case, the signal transmission to or from the lower semiconductor chip is adversely influenced.
Referring to
FIG. 1
, a structure of stacked semiconductor chips includes a substrate
10
, a lower semiconductor chip
12
, an upper semiconductor chip
14
, a plurality of wirings
16
, and an isolation layer
18
. The lower semiconductor chip
12
is located on the substrate
10
. The isolation layer
18
is located on the lower semiconductor chip
12
. The upper semiconductor chip
14
is stacked on the isolation layer
18
. That is, the upper semiconductor chip
14
is stacked above the lower semiconductor chip
12
with the isolation layer
18
interposed between the semiconductor chips
12
and
14
. Thus, a proper gap
20
is formed between the lower semiconductor chip
12
and the upper semiconductor chip
14
. According to this structure, the plurality of wirings
16
can be electrically connected to the edge of the lower semiconductor chip
12
. Furthermore, when stacking the upper semiconductor chip
14
above the lower semiconductor chip
12
, the plurality of wirings
16
connecting the substrate
10
to the lower semiconductor chip
12
are free from being pressed, or the plurality of wirings
16
and the lower semiconductor chip
12
are free from being short-circuited.
However, the above-mentioned structure has the disadvantages to be described hereinbelow. During the manufacturing processes, the isolation layer
18
has to be manufactured in advance, and then, it is adhered to the lower semiconductor chip
12
. Thereafter, the upper semiconductor chip
14
is adhered on the isolation layer
18
. As a result, the manufacturing processes are complicated, and the manufacturing costs are high.
Furthermore, if the bonding pads of the lower semiconductor chip
12
are formed at the central portion thereof, it is impossible for the semiconductor chips to be stacked.
As shown in
FIG. 2
, bonding pads
22
are formed at the central portion of the lower semiconductor chip
23
. In this case, the upper semiconductor chip
24
presses the wirings
25
to contact the edge of the lower semiconductor chip
23
, thereby adversely influencing the signal transmission or causing the above-mentioned elements to be short-circuited.
To solve the above-mentioned problems, it is necessary for the invention to provide a stacked semiconductor package structure having films and method for manufacturing the same, in order to facilitate the manufacturing processes and lower down the manufacturing costs.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a stacked structure of a semiconductor means and method for manufacturing the same, so as to facilitate the stacking processes of the semiconductor means and improve the manufacturing speed.
It is therefore another object of the invention to provide a stacked structure of a semiconductor means and method for manufacturing the same, so as to avoid bad signal transmission when stacking the semiconductor chips.
It is therefore still another object of the invention to provide a stacked structure of a semiconductor means and method for manufacturing the same, so as to prevent the wires connected to the lower integrated circuit from being damaged by the upper integrated circuit, thereby facilitating the manufacturing processes.
To achieve the above object, one aspect of the present invention comprises a substrate, a lower semiconductor chip, an adhered glue layer, a plurality of wires and an upper semiconductor chip. The substrate having a first surface and a second surface opposite to the first surface, the first surface formed with signal input terminals, then, the second surface formed with signal output terminals for electrically connected to the printed circuit board.
a lower semiconductor chip having a upper surface and a lower surface, the central part of the upper surface formed with a plurality of bonding pads:
a adhered glue resin located between the substrate and the lower semiconductor for adhering the lower surface of the semiconductor to the first surface of the substrate. The overflow glue of the adhered glue resin covered over the periphery of the lower semiconductor chip:
a plurality of wires each having a first end and second end away from the first end, the first end being electrically connected to the bonding pads of the lower semiconductor chip, the second end being electrically connected to the signal input terminals in order to signals from the lower semiconductor chip are capable of being transmitted to the substrate.
a upper semiconductor chip located on the upper surface of the semiconductor chip to stack above the lower semiconductor chip and electrically connected to the signal input terminals of the substrate.
Thus, while the upper semiconductor stacked with the lower semiconductor, the overflow glue of the adhered glue layer covered the upper surface of the lower semiconductor for protecting the plurality of wires, so as to avoid bad signal transmission when stacking the semiconductor means.
REFERENCES:
patent: 5804874 (1998-09-01), An et al.
patent: RE36613 (2000-03-01), Ball
patent: 6087718 (2000-07-01), Cho
patent: 6100594 (2000-08-01), Fukui et al.
patent: 6180881 (2001-01-01), Isaak
patent: 6271598 (2001-08-01), Vindasius et al.
patent: 6316727 (2001-11-01), Liu
Peng Chen Pin
Tsai Meng Ru
Wu Ji-chen
Yeh Nai Hua
Kingpak Technology Inc.
Picardat Kevin M.
Pro-Techtor Inter-national Services
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