Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2002-03-13
2002-10-29
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
Reexamination Certificate
active
06472736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a stacked structure for memory chips, and more particularly to a stacked structure having high memory capacity and signal transmission speed.
2. Description of the Related Art
In order to increase the memory capacity of a single package body, two or more memory chips are stacked and packaged.
Referring to
FIG. 1
, a conventional stacked structure for memory chips includes a substrate
10
, a lower memory chip
12
, and an upper memory chip
14
. The substrate
10
has a central portion formed with a slot
16
. The lower memory chip
12
is arranged on the substrate
10
and formed with a plurality of bonding pads
18
exposed via the slot
16
. The bonding pads
18
are electrically connected to the substrate
10
via a plurality of wires
20
. Thus, signals from the lower memory chip
12
can be transmitted to the substrate
10
. The upper memory chip
14
is arranged on the lower memory chip
12
in a back-to-back manner with respect to the lower memory chip
12
. The upper memory chip
14
also has a central portion formed with bonding pads
22
electrically connected to the substrate
10
via a plurality of wires
24
, so that signals can be transmitted to the substrate
10
.
In the above-mentioned stacked structure for memory chips, the bonding pads of the memory chips are formed on the central portions. Therefore, when the upper memory chip
14
are electrically connected to the substrate
10
via the plurality of wires
24
, the radian of each wire
24
is greater. Accordingly, the length of each wire
24
is longer, the signal transmission is not easy, and the volume of the package body is larger. In this case, the package cannot be made light, thin, short, and small. Furthermore, since the length of each wire
24
is longer, the wires
24
are liable to falling down to contact the surface of the upper memory chip
14
, and the condition of bad signal transmission effect or short-circuit may easily occur.
In view of the above-mentioned problems, it is therefore an object of the invention to provide a stacked structure for memory chips capable of overcoming the disadvantages of the conventional structure for memory chips.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a stacked structure for memory chips capable of shortening the signal transmission distance and improving the signal transmission effect.
Another object of the invention is to provide a stacked structure for memory chips capable of enhancing the stacked quality and yield.
Still another object of the invention is to provide a stacked structure for memory chips, which is easily made and more utility.
Yet still another object of the invention is to provide a stacked structure for memory chips capable of reducing the package volume, which is light, thin, short, and small.
To achieve the above-mentioned objects, a stacked structure for memory chips is provided. The structure includes a substrate, a lower memory chip, an upper memory chip, and an insulation medium. The substrate has an upper surface, a lower surface and a slot penetrating through the substrate from the upper surface to the lower surface. The lower memory chip has a central portion formed with a plurality of bonding pads. The lower memory chip is arranged on the upper surface of the substrate. The plurality of bonding pads is exposed via the slot of the substrate, and the bonding pads are electrically connected to the lower surface of the substrate via a plurality of wires. The upper memory chip has a central portion formed with a plurality of bonding pads. The upper memory chip is arranged on the lower memory chip in a back-to-back manner with respect to the lower memory chip so that the plurality of bonding pads of the upper memory chip faces upwards. The insulation medium has a central portion formed with a slot. The plurality of bonding pads of the upper memory chip is exposed via the slot of the insulation medium. The insulation medium is formed with a plurality of traces electrically connecting to the bonding pads of the upper memory chip and the upper surface of the substrate via a plurality of wires.
Accordingly, the length and radian of each wire can be reduced so that a better signal transmission effect and a smaller package volume can be obtained.
REFERENCES:
patent: 6265766 (2001-07-01), Moden
patent: 6265768 (2001-07-01), Su et al.
patent: 6343019 (2002-01-01), Jiang et al.
patent: 6218731 (2002-04-01), Huang et al.
patent: 6388313 (2002-05-01), Lee et al.
patent: 54-150078 (1979-11-01), None
Peng Chen Pin
Yeh Nai Hua
Clark Jasmine J B
Kingpak Technology Inc.
Pro-Techtor Inter-national Services
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