Stacked solid via formation in integrated circuit systems

Details Stacked solid via formation in integrated circuit systems Stacked solid via formation in integrated circuit systems

1989-06-01

1991-10-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437203, 437228, 437208, 437246, 437915, 437978, 156643, 156645, 156650, 148DIG164, H01L 21283, H01L 21312

Patent

active

050554255

ABSTRACT:
A method of forming solid copper vias in a dielectric layer permits stacked up vias in a multi-layer multi-chip carrier. An conducting layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in a photoresist layer over said lines is filled with copper by electroplating to form a solid via. The via can be polished until its top is flat. Using a photoresist mask, the conductive layer used for electroplating is removed between the lines. A dielectric layer is then formed over the lines and via. A bulge in the dielectric over the via is removed by etching through an aperture defined in a photoresist layer, which is then stripped. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked up vias.

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