Stacked silicon die carrier assembly

Details Stacked silicon die carrier assembly Stacked silicon die carrier assembly

1994-07-26

1995-07-18

Ledynh, Bot L.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361744, 361790, 257686, 257777, 257693, 257694, 437208, 437915, 174 524, H05K 700, H01L 2118

Patent

active

054347459

ABSTRACT:
Disclosed is a stacked die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips. The carrier is constructed from a metalized substrate onto which the chip is attached. The chip is wire bonded to the conductor pattern on the substrate. Each conductor then is routed to the edge of the substrate where it is connected to a half-circle of a metalized through hole. A frame is attached on top of this substrate. This frame has also a pattern of half-circle metalized through holes that aligns with the holes on the bottom substrate. The combination of the bottom substrate with the silicon die, and the frame on top, forms a basic stackable unit. Several such units can be stacked and attached on top of each other. The top unit can finally be covered with a ceramic lid that also has a matching half-circle metalized through hole pattern along its edge. To electrically interconnect the stacked assembly conductive epoxy can be applied in the grooves formed by the aligned half-circle plated through holes.

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R. T. Crowley, E. J. Ver daman, "3-D Multichip Packaging for Memory Modules", 1994 ISHM Proceedings.
"Dense-Pac 3-D Technology", pp. 3494-3499 and 3505-3508 from IC Master 1993.

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