Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
2000-07-26
2003-07-15
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
Reexamination Certificate
active
06594132
ABSTRACT:
FIELD OF THE INVENTION
This invention is directed to electronic circuits, and more particularly to electrostatic device protection circuits using stacked silicon controlled rectifiers.
BACKGROUND OF THE INVENTION
Integrated circuits, particularly integrated circuits formed of MOS transistors, are vulnerable to damage from electrostatic discharge (ESD), such as high voltage transients in electrical equipment. In some equipment, high voltage transients may have positive and/or negative peak levels of 100 volts or more and may have a duration of several microseconds. High voltage electrostatic discharge (ESD) transients can also result from a user becoming electrostatically charged, for example, by friction or by induction and touching equipment controls. These transients may have peak voltages of several thousand volts.
As integrated circuits have increased in size to include a larger number of circuit elements, the geometry of the circuit elements has decreased in order to minimize the overall size of the IC. With decreasing geometries of the circuit elements, providing adequate levels of ESD protection has become increasingly more difficult. In MOS circuits the gate oxide thickness has decreased to below 10 nanometers (nm), and breakdown voltages are often less than 10 volts (V). Fowler Nordheim (FN) tunneling through the oxide can occur at voltages as low as 7 V. Device junction breakdown voltages, which are often used to protect the sensitive gate oxide directly, or to trigger a protection structure such as a snap-back device, have remained high to minimize hot carrier generation. In many cases, the minimum junction breakdown voltage is above the gate oxide breakdown voltage.
Many attempts have been made to protect semiconductor devices, such as bipolar transistors, field effect devices, and integrated circuits, from damage due to voltage and current transients. Such protection devices have commonly taken the form of diode or transistor circuits incorporated on the integrated circuit chip for internal transient protection. Protection circuits advantageously utilizing silicon controlled rectifier (SCR) arrangements are also known, for example, see Avery, U.S. Pat. No. 5,615,074; Avery, U.S. Pat. No. 5,343,053; Yu, U.S. Pat. No. 5,986,307; and Avery, U.S. Pat. No. 5,072,273.
One such arrangement, as shown in
FIG. 1
, involves stacked SCRs, see Avery, U.S. Pat. No. 5,615,074. A stacked SCR arrangement can be placed in parallel with a circuit to provide ESD protection of that circuit. In this arrangement multiple SCRs are connected in series, coupled to a triggering mechanism. The triggering mechanism causes the series of SCRs to conduct upon being triggered by a transient voltage. This voltage, also referred to as the ESD potential, is the voltage that can damage the circuit being protected. The number of SCRs in the series determines, in part, the electrical potential across the series (clamping voltage) during conduction. Stacked SCRs are used to accommodate higher trigger and clamping voltages. Stacked configurations can provide protection from higher voltages and prevent the ESD protection circuit from triggering and clamping at too low a voltage. This is desirable to prevent an ESD protection circuit from conducting unnecessarily due to spurious low voltage transients.
FIG. 1
is a circuit diagram of an exemplary configuration of stacked SCRs used to provide ESD protection. Voltages V+ and V− in
FIG. 1
represent positive and negative supply voltages, respectively, to circuit
100
. Circuit
100
is a circuit to be protected. Circuit
100
is placed in parallel with the stacked SCRs configuration. In
FIG. 1
, three SCRs
20
,
10
, and
12
, are connected in series between the supply voltages V+ and V−. A triggering mechanism, comprising zener diode
2
and resistor
4
is connected in parallel across the series SCRs. The anode
24
of SCR
20
is connected to the positive supply voltage, V+, and the cathode
3
of SCR
20
is connected to the anode
9
of SCR
10
. The cathode
5
of SCR
10
is connected to the anode
11
of SCR
12
. The cathode
7
of SCR
12
is connected to the supply voltage, V−. G
2
gate
6
and G
2
gate
8
are connected to the negative supply voltage, V−, so as to turn SCRs
10
and
12
on. G
1
gates
14
,
16
, and
18
are connected to ground. SCR
20
has its G
2
gate
22
connected to the positive power supply, V+, through resistor
4
to keep SCR
20
in an off state. A zener diode
2
is connected between the negative supply voltage, V−, and G
2
gate
22
of SCR
20
. In normal operation of circuit
100
, SCR
20
is turned off and only a small leakage current flows through the zener diode
2
. Also, SCRs
10
and
12
are turned on. When a transient voltage is applied to the supply voltage, the zener diode
2
holds gate
22
at the voltage of the zener diode
2
. The current flowing through zener diode
2
also flows through resistor
4
. This current causes a voltage drop across resistor
4
. The voltage across resistor
4
is also the voltage across G
2
gate
22
and anode
24
of SCR
20
. Once the voltage drop across resistor
4
becomes greater than Vbe, SCR
20
turns on. Vbe is the voltage that causes conduction across a p
junction within SCR
20
(e.g., 0.7 volts). When SCR
20
turns on, the transient voltage is clamped, providing ESD protection.
Typically, in this stacked configuration, the G
1
gates of each SCR are formed within a common well, such as a P-Well, within the substrate of an integrated circuit. One disadvantage of a stacked configuration using a common well region is that, because the G
1
gates are tied together, the turn on times are slow. In some cases, the current used to rapidly trigger the SCRs into the on state implies the use of a large area trigger device. Thus, a significant advantage to the art would be provided by a stacked configuration of SCRs not requiring the gates of multiple SCRs to be electrically coupled to a common well, as this essentially forces the gates of the upper SCRs,
20
and
10
, to be reversed biased with respect to their respective cathodes.
SUMMARY OF THE INVENTION
The present invention comprises an electrostatic protection circuit formed from a plurality of silicon controlled rectifiers connected in series. Each silicon controlled rectifier has a first gate, a second gate, a cathode, and an anode. The anode of the first silicon controlled rectifier is electrically coupled to the first end of the series connection and the cathode of the last silicon controlled rectifier is electrically coupled to the second end of the series connection. The first and second gates of each silicon controlled rectifier, except the last silicon controlled rectifier, are cross coupled. The circuit is activated by a triggering mechanism that is electrically coupled to one of the gates of the last silicon controlled rectifier.
REFERENCES:
patent: 4130767 (1978-12-01), Okuhara et al.
patent: 4567500 (1986-01-01), Avery
patent: 5072273 (1991-12-01), Avery
patent: 5274262 (1993-12-01), Avery
patent: 5343053 (1994-08-01), Avery
patent: 5400202 (1995-03-01), Metz et al.
patent: 5572394 (1996-11-01), Ker et al.
patent: 5615074 (1997-03-01), Avery
patent: 5663860 (1997-09-01), Swonger
patent: 5932916 (1999-08-01), Jung
patent: 5959332 (1999-09-01), Ravanelli et al.
patent: 5986307 (1999-11-01), Yu
patent: 6016002 (2000-01-01), Chen et al.
Burke William J.
Kitov Z.
Sarnoff Corporation
Sircus Brian
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