Stacked semiconductor packaging device

Details Stacked semiconductor packaging device Stacked semiconductor packaging device

2002-03-26

2003-11-18

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000, C257S723000, C257S690000, C257S784000, C257S786000, C257S778000, C257S737000

Reexamination Certificate

active

06650008

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a stacked semiconductor packaging device, and more particularly relates to stacked multi-chip packaging device.
2. Description of the Prior Art
Recent years, semiconductor devices are constructed on the same wafer. When the devices are sawed into individual rectangular units, each takes the form of an integrated circuit (IC) chip. In order to interface a chip with other circuitry, normally it is mounted on a lead-frame chip paddle or a multi-chip module substrate.
In many cases, multi-chip devices can be fabricated faster and more cheaply than a corresponding single IC which incorporates the same or different functions. Current multi-chip module construction typically consists of a printed circuit board substrate to which a series of separate components are directly attached. This technology is advantageous because of the increase in circuit density achieved. With increased density comes improvements in signal propagation speed and overall device weight. While integrated circuit density increases at a significant rate, the interconnection density has become a significant limiting factor in the quest for miniaturization.
U.S. Pat. No. 5,012,323 discloses a pair of rectangular integrated-circuit dice mounted on opposite sides of the lead-frame. An upper, smaller chip is back-bonded to the upper surface of the lead fingers of the lead-frame via an adhesively coated, insulated film layer. The lower, slightly larger chip is face-bonded to the lower surface of the lead extensions within the lower lead-frame chip-bonding region via a second, adhesively coated, insulating, film layer. The wire-bonding pads on both the upper chip and the lower chip are interconnected with the ends of their associated lead extensions by gold or aluminum wire. The lower chip needs to be slightly larger for accessibility to the chip pads from above allowing gold wire connections to the lead extensions or fingers.
U.S. Pat. No. 5,721,452 discloses an offset chip stacked arrangement with at least one upper level chip having a width which is less than the distance separating the opposing bonding pads of the underlying chip. The upper chip is suspended above the lower chip on one or more pillars and rotated within a plane parallel to the lower chip through an angle. Once the dice are fixed in this manner, the entire assembly is subjected to the wire bonding process with all of the bonds being made in the same step.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a stacked multi-chip device. The stacked multi-chip device consists of chips with face-to-face stacked arrangement for reducing the whole stacked height.
It is another object of the present invention to provide an assembly of semiconductor devices. The assembly of semiconductor devices has stacked chips with cross arrangement without interference of bonding pads with each another.
It is further object of the present invention to provide a stacked semiconductor packaging device. The stacked semiconductor packaging device has the minimum overall height of the assembly, and has facilitating ease and efficiency of wire bonding.
In the present invention, a stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is, offset or rotated, stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.


REFERENCES:
patent: 5012323 (1991-04-01), Farnworth
patent: 5229960 (1993-07-01), De Givry
patent: 5721452 (1998-02-01), Fogal et al.
patent: 5760478 (1998-06-01), Bozso et al.
patent: 5808878 (1998-09-01), Saito et al.
patent: 6084308 (2000-07-01), Kelkar et al.

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