Stacked semiconductor memory device

Details Stacked semiconductor memory device Stacked semiconductor memory device

2010-05-21

2011-12-13

Picardat, Kevin M (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S773000, C257S777000

Reexamination Certificate

active

08076766

ABSTRACT:
A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.

REFERENCES:
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patent: 7494846 (2009-02-01), Hsu et al.
patent: 7548444 (2009-06-01), Matsui et al.
patent: 2005/0082664 (2005-04-01), Funaba et al.
patent: 2004-327474 (2004-11-01), None
patent: 2005-191172 (2005-07-01), None
patent: 2006-13337 (2007-01-01), None

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