Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Patent
1997-01-17
1999-09-14
Chaudhun, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
257686, 438458, 438464, 438114, H01L 2348, H01L 2352, H01L 2940
Patent
active
059527250
ABSTRACT:
A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair. At least one face side of the die pair (attachment side) may have an array of minute solder balls or small pins disposed thereon for attachment and electrical communication of the die to at least one substrate such as a printed circuit board or leadframe. The die pair face opposite the substrate attachment side (opposing side) and may have a plurality of bond pads. Bond wires or TAB leads are attached between bond pads on the opposing side and corresponding conductive trace or lead ends on the substrate. Alternately, both the attachment side and opposing side may have an array of minute solder balls or small pins for respective attachment to two facing substrates on opposite sides of the die pair.
REFERENCES:
patent: 4264917 (1981-04-01), Ugon
patent: 4472875 (1984-09-01), Christian et al.
patent: 4826787 (1989-05-01), Muto et al.
patent: 4862245 (1989-08-01), Pashby et al.
patent: 5012323 (1991-04-01), Farnworth
patent: 5019943 (1991-05-01), Fassbender et al.
patent: 5051865 (1991-09-01), Kato
patent: 5104820 (1992-04-01), Go et al.
patent: 5146308 (1992-09-01), Chance et al.
patent: 5147815 (1992-09-01), Casto
patent: 5229647 (1993-07-01), Gnadinger
patent: 5239198 (1993-08-01), Lin et al.
patent: 5252857 (1993-10-01), Kane et al.
patent: 5266833 (1993-11-01), Capps
patent: 5291061 (1994-03-01), Ball
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5331235 (1994-07-01), Chun
patent: 5399898 (1995-03-01), Rostoker
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5426072 (1995-06-01), Finnila
patent: 5432681 (1995-07-01), Linderman
patent: 5438224 (1995-08-01), Papageorge et al.
patent: 5466634 (1995-11-01), Beilstein, Jr. et al.
patent: 5471369 (1995-11-01), Honda et al.
patent: 5483024 (1996-01-01), Russell et al.
patent: 5484959 (1996-01-01), Burns
patent: 5495398 (1996-02-01), Takiar et al.
patent: 5547906 (1996-08-01), Badehi
patent: 5567654 (1996-10-01), Beilstein, Jr. et al.
patent: 5675180 (1997-10-01), Pedersen et al.
Cao Phat X.
Chaudhun Olik
Micro)n Technology, Inc.
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