Stacked semiconductor device structure

Details Stacked semiconductor device structure Stacked semiconductor device structure

2003-03-04

2004-08-17

Cuneo, Kammie (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S723000, C257S724000

Reexamination Certificate

active

06777798

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a surface mount type stacked semiconductor device structure including a plurality of semiconductor devices each having a package and an outer lead, in which space for mounting the semiconductor devices on a system appliance can be reduced and capacity of the semiconductor devices can be increased.
2. Description of the Prior Art
Hereinafter, four examples of prior art memory modules in which their capacities are made twice are described with reference to
FIGS. 28
to
31
, respectively. Firstly, in a prior art memory module
130
shown in
FIG. 28
, a semiconductor device
132
formed by an ordinary single chip is mounted on each of opposite faces of a printed wiring board
133
by outer leads
132
a
extending straight horizontally from opposite sides of the semiconductor device
132
. The memory module
130
is mounted on a substrate
120
for a system appliance by solder balls
39
provided on a lower face of the printed wiring board
133
.
Secondly, in a conventional memory module
140
shown in
FIG. 29
, two packages
142
each having gull wing outer leads or L type outer leads
144
are stacked on each other through a small connecting substrate
143
. By soldering the L type outer lead
144
of the lower package
142
to the substrate
120
for the system appliance, the memory module
140
is mounted on the substrate
120
for the system appliance.
Thirdly, in a known memory module
150
shown in
FIG. 30
, L type outer leads
153
of a lower package
152
and outer leads
155
of an upper package
154
are directly connected to each other. By soldering the L type outer leads
153
of the lower package
152
to the substrate
120
for the system appliance, the memory module
150
is mounted on the substrate
120
for the system appliance.
Fourthly, in a prior art memory module
160
shown in
FIG. 31
, two semiconductor chips
163
are stacked on each other in a resinous package
162
. By soldering L type outer leads
164
of the resinous package
162
to the substrate
120
for the system appliance, the memory module
160
is mounted on the substrate
120
for the system appliance.
However, in the constructions of the above described prior art memory modules and in the methods of mounting the above mentioned prior art memory modules on the substrate
120
for the system appliance, such drawbacks are incurred that the number of stacking of the semiconductor devices
132
in
FIG. 28
, the number of stacking of the packages
142
in
FIG. 29
, the number of stacking of the packages
152
and
154
in FIG.
30
and the number of stacking of the semiconductor chips
163
in the resinous package
162
in
FIG. 31
are physically limited and reduction of area for mounting the memory module on the substrate
120
for the system appliance is restricted by size of these semiconductor devices.
SUMMARY OF THE INVENTION
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawbacks of prior art, a surface mount type stacked semiconductor device structure including a plurality of semiconductor devices, in which space for mounting the semiconductor devices on a system appliance can be reduced and capacity of the semiconductor devices can be increased.
In order to accomplish this object of the present invention, a stacked semiconductor device structure according to the present invention comprises: a plurality of semiconductor modules each of which includes a substrate and at least one semiconductor device mounted on the substrate; a stacking means for stacking the semiconductor modules on one another; and a surface mount means for surface mounting on a further substrate for a system appliance the semiconductor modules stacked on one another by the stacking means.


REFERENCES:
patent: 5570274 (1996-10-01), Saito et al.
patent: 5744862 (1998-04-01), Ishii
patent: 5982026 (1999-11-01), Tsunoda
patent: 6038132 (2000-03-01), Tokunaga et al.
patent: 6160718 (2000-12-01), Vakilian
patent: 63-073694 (1988-04-01), None
patent: 63-114245 (1988-05-01), None
patent: 02-134890 (1990-05-01), None
patent: 04-276649 (1992-10-01), None
patent: 06-177501 (1994-06-01), None
patent: 06-314885 (1994-11-01), None
patent: 06-334294 (1994-12-01), None
patent: 07-022727 (1995-01-01), None
patent: 8-153747 (1996-06-01), None
patent: 9-121017 (1997-05-01), None
patent: 9-252083 (1997-09-01), None
patent: 09-270575 (1997-10-01), None
patent: 10-173122 (1998-06-01), None
patent: 11-40745 (1999-02-01), None
patent: 11-214611 (1999-08-01), None
patent: 2000-124400 (2000-04-01), None
patent: 2000-156460 (2000-06-01), None
patent: 2000-156465 (2000-06-01), None
patent: 2000-252419 (2000-09-01), None
patent: 2000-307055 (2000-11-01), None
patent: 2001-68594 (2001-03-01), None

Affiliated with

Also associated with

Rating

Stacked semiconductor device structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked semiconductor device structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked semiconductor device structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3334464