Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2001-03-07
2002-10-29
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S686000, C257S777000
Reexamination Certificate
active
06472734
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-063873, filed Mar. 8, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that is favorable for stacking semiconductor packages and a method for manufacturing the semiconductor device.
The market for small-sized memory cards equipped with a flash memory, which are used as digital still cameras and personal digital assistants, has recently increased fast. Particularly in the field of digital cameras, the memory cards are going mainstream and establishing themselves as an alternative to MD and floppy disks.
Against the above background, it is required that the small-sized memory cards, which are constituted of only flash memories, should increase in capacity, reduce in size and decrease in cost. Various structures for packaging and mounting memory ICs are therefore proposed.
Generally, a method of soldering a thin mold package such as TSOP (thin small outline package) to a base board and a method of directly connecting a bare chip to a base board using wire bonding, flip chip bonding or the like are adopted. Since, however, the storage capacity depends upon the chip size, the packaging technique of stacking chips three-dimensionally should be adopted to increase the capacity further.
FIG. 5
shows a prior art semiconductor device
10
having a stacked packaging structure wherein four semiconductor elements, which are packaged by a so-called TAB (tape automated bonding) method, are connected to a base board.
In the semiconductor device
10
, four semiconductor elements
13
are each connected to a given portion of a copper-made wiring pattern
12
, which is formed on a polyimide wiring board
11
, through a gold-made bump
14
by thermocompression bonding, ultrasonic bonding or the like. Each semiconductor element
13
is sealed with resin
15
, such as epoxy resin, so as to cover its top and sides. After the four semiconductor elements
13
are packaged in the same manner, these four packages are stacked on a connection land
17
of a base board
16
, and leads
18
for connecting the packages to an external device are connected to each other in sequence or together by means of a connection member
19
, e.g., solder.
In order to connect the four packages to the base board
16
, the connecting leads
18
need to be formed. In this case, the leads should be formed into different shapes because they need to be aligned with their respective levels of the four packages.
When four packages are stacked on one another, the following problem occurs: Four different forming molds are required and the forming models produce four different packages. Therefore, the process control is complicated and the manufacturing cost is high.
When four memory ICs are stacked one on another, the following problem occurs: All terminals except a chip select terminal serve as a common terminal and thus four connecting leads
18
should be stacked and connected to each other. In this case, a misalignment of the stacked leads easily causes poor connection and reduces the yield. In order to enhance the yield, there is a method of connecting the leads
18
to the baseboard
16
such that the leads
18
are displaced from each other. Since, however, four connecting leads
18
are arranged in parallel, the area of connecting portions necessary for packaging is simply quadrupled, and a narrow pitch is difficult to obtain.
The prior art stacked packaging structure has another problem that a semiconductor device is difficult to miniaturize since a space for forming the connecting leads
18
is required.
In order to achieve the above miniaturization and narrow pitch, there is a method of connecting the respective packages using not connecting leads but bumps.
FIG. 6
is a view illustrating a semiconductor device
20
in which an IC chip is mounted on a thin printed board by flip chip bonding.
In the semiconductor device
20
, four semiconductor elements
23
are each connected to a given portion of a copper-made wiring pattern
22
, which is formed on a polyimide wiring board
21
, through a gold-made bump
24
by flip chip bonding. Each semiconductor element
23
is sealed with resin
15
, such as epoxy resin, so as to cover a space between the element
23
and the wiring board
21
and the sides of the element
13
. After the four semiconductor elements
23
are packaged in the same manner, these four packages are stacked on a connection land
27
of a base board
26
with a connecting member
28
, e.g., a solder ball, interposed therebetween. Connection lands
21
a
are formed on both sides of the wiring board
21
and connected to each other by reflow and thermocompression bonding.
When the respective packages are connected by solder, a solder ball can be employed or solder paste can be formed by printing as a solder supply method. In either case, the process is stabilized if the packages are connected using solder that is melted into a bump by reflow.
However, the following problem arises: Passing the semiconductor elements through a reflow furnace exercises an adverse influence on the stability and reliability of the subsequent process, e.g., damage to the connecting portions of the semiconductor elements and a warp of the wiring board.
The above-described prior art semiconductor device and its manufacturing method have the following problems: Since the stacked packages need to vary in shape from one to another, the process control is complicated. Since, moreover, the stacked packages are connected by leads, miniaturization and a narrow pitch are difficult to obtain in the semiconductor device.
When the packages are connected by bumps, they need to pass through the reflow furnace, which exercises an adverse influence on the stability and reliability of the subsequent process, e.g., damage to the connecting portions of the elements and a warp of the wiring board. When the packages are connected by plated bumps, solder is unmelted or overflows and a solid metal bump made of, e.g., copper is hardly deformed, thus making the connection of the packages unstable.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that can be decreased in size and pitch and manufactured in a stable process.
According to one aspect of the present invention, there is provided a semiconductor device in which a first semiconductor element and a second connecting section having a first external connection land are arranged on a first wiring board toward a second wiring board, a third connecting section is formed on the surface of the second wiring board toward the first wiring board and arranged opposite to the first external connection land, the second connecting section includes the first external connection land, the third connecting section is arranged opposite to the first external connection land and includes a second external connection land that is smaller than the first external connection land, and the second and third connecting sections are formed such that a combined thickness thereof provides a given space between the first semiconductor element and the second wiring board.
According to the present invention described above, since the connecting sections for connecting the wiring boards are formed thick, the wiring boards can be stacked by a simple process without forming any new bumps. The semiconductor device of the present invention can be thinned more than a semiconductor device that is manufactured using newly-added bumps. Consequently, the device can be decreased in size and pitch and manufactured in a stable process without decreasing in yields.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obt
Arakawa Masayuki
Saito Yasuhito
Watanabe Naotake
Clark Jasmine J B
Kabushiki Kaisha Toshiba
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