Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-09-22
2002-03-26
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S686000
Reexamination Certificate
active
06362529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stacked semiconductor device (e.g., a three-dimensional LSI). In particular, it relates to a structure for mutually and electrically connecting stackable semiconductor chips to be stacked.
2. Description of Related Art
Today, a complex semiconductor device or module combining a plurality of semiconductor chips (LSI chips) and connecting them to a circuit board using a wire bonding method is generally used to fill demands for greater functions.
However, such a device may delay a signal transmitted among the plural semiconductor chips depending on the length of wirings connecting them so that it cannot sufficiently keep up with improvement in operation speed of the semiconductor chips.
For such a problem, shortening the wirings in the complex semiconductor device as much as possible is an effective solution. Accordingly, a flip-chip bonding method is generally employed to directly connect electrodes of the semiconductor chips to the circuit board instead of the wire bonding method.
However, the signal transmission may possibly be delayed even in the flip-chip bonded device because the signal among the semiconductor chips is transmitted through the circuit board.
As a solution of this problem, a semiconductor device formed by stacking semiconductor chips on each other is commonly known as a three-dimensional LSI (see Japanese Unexamined Patent Publication No. HEI 5(1993)-63137, for example).
In such a stacked semiconductor device, the semiconductor chips are mutually connected in the following manner.
First, through holes are partially formed in the semiconductor chip and a conductive material is filled in the through holes to form penetrating electrodes, which are exposed on the front and back surfaces of the semiconductor chip. The penetrating electrodes define bump electrodes (projecting electrodes) or pad electrodes on end surfaces thereof.
Then, the bump (or pad) electrodes of one semiconductor chip abut those of another semiconductor chip to mutually connect the two chips.
However, the stacked semiconductor devices of the prior art have been suffering from the following drawbacks.
1) The stacked semiconductor chips are connected with each other through series of penetrating electrodes which are put on top of each other, so that only one signal can be transmitted through one series of penetrating electrodes. This prevents the flexibility in design of the wirings for connecting the semiconductor chips.
2) The electrodes of the stacked semiconductor chips are formed only on necessary regions according to the required function. Therefore the arrangement of the electrodes must be designed for every semiconductor device. This makes production efficiency poor when various types of stacked semiconductor devices are produced.
SUMMARY OF THE INVENTION
The present invention has been achieved in view of these circumstances, and provides a stacked semiconductor device having improved flexibility in design of the wirings for connecting the semiconductor chips. It is free from necessity to change the arrangement of the electrodes connecting between the semiconductor chips for every semiconductor device, by separately forming a penetrating electrode and a bump or pad electrode in each of the stacked semiconductor chips and selectively connecting the electrodes to each other through an optional wiring pattern. According to this, the production efficiency is improved when various types of stacked semiconductor devices are produced.
The present invention provides a stacked semiconductor device comprising: a plurality of stacked semiconductor chips, each of the semiconductor chips including a penetrating electrode which penetrates from a front surface to a back surface of the semiconductor chip, a first electrode formed on the front surface, a second electrode formed on the back surface and wiring patterns formed on the front and back surfaces for selectively connecting the first and second electrodes through the penetrating electrode, the first electrode of a lower semiconductor chip abutting the second electrode of an upper semiconductor chip with respect to adjacent two of the stacked semiconductor chips.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 6002177 (1999-12-01), Gaynes et al.
patent: 19918671 (2000-11-01), None
patent: 0915516 (1999-05-01), None
patent: A563137 (1993-03-01), None
Sumikawa Masato
Tanaka Kazumi
Potter Roy
Sharp Kabushiki Kaisha
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