Stacked semiconductor chips

Details Stacked semiconductor chips Stacked semiconductor chips

2007-09-21

2010-12-28

Lindsay, Jr., Walter L (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S613000, C257S686000, C257S777000, C257SE21499, C257SE23179

Reexamination Certificate

active

07858440

ABSTRACT:
Stacked semiconductor chips are disclosed. One embodiment provides an array of first semiconductor chips, covering the array of the first semiconductor chips with a mold material, and placing an array of second semiconductor chips over the array of the first semiconductor chips. The thicknesses of the second semiconductor chips is reduced. The array of the first semiconductor chips are singulated by dividing the mold material.

REFERENCES:
patent: 2003/0112610 (2003-06-01), Frankowsky et al.
patent: 2003/0203540 (2003-10-01), Hur
patent: 2004/0036164 (2004-02-01), Koike et al.
patent: 1801866 (2007-06-01), None
Amkor Technology, Amkor Confidental/Proprietary Business Information, Sep. 2005, CSCAN.
“Embedded Wafer Level Ball Grid Array (eWLB)”, M. Brunnbauer, et al., 2006 Electronics Packaging Technology Conference, 2006 IEEE.
“Neo-Stacking Technology”, Keith D. Gann, Irvine Sensors Corporation, published in the Dec. 1999 issue of HDI Magazine, 1999 Miller Freeman, Inc.

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