Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
1998-03-23
2001-02-13
Williams, Alexander O. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S723000, C257S730000, C257S777000, C257S692000, C257S693000, C257S738000, C257S700000, C257S758000
Reexamination Certificate
active
06188129
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stackable semiconductor chip, stacked semiconductor chip package and fabrication methods thereof.
2. Description of the Conventional Art
Generally, the three-dimensional chip stacking technique is a key technique for developing a high capacity and small-sized semiconductor chip package. This technique is disclosed in U.S. Pat. No. 5,104,820 and U.S. Pat. No. 5,279,991.
FIG. 1
illustrates a portion of the three-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,104,820. As shown, a wafer
2
is divided into a plurality of semiconductor chips
11
by separation lines
4
. The pads
12
for one of the semiconductor chips
11
is also shown. A conductive wire
13
is connected to each one of the pads
12
, and terminates in a realigned pad
14
. In this manner, the pads
12
are realigned. Unfortunately, realigning the pads
12
requires forming conductive wires
13
over adjacent semiconductor chips
11
, rendering those chips unusable. Thus, the yield for the wafer
2
is also significantly reduced.
Next, the semiconductor chips
11
are cut along the separation lines
4
. The semiconductor chips
11
with conductive wires
13
formed thereon, however, are not separated from the semiconductor chip
11
having the pads
12
; the conductive wires
13
being connected to the pads
12
. The thusly separated chips
11
are stacked and formed into a module. Then, the side surfaces of each chip
11
in a module are insulated from the sides of the other chips
11
.
The insulation of the sides of each chip will now be explained in more detail. In the module in which padre-aligned chips are stacked in multiple layers, the side surfaces of each chip are etched except for end portions of the conductive wires
13
, and a polymer insulation is filled in the etched portions; thus insulating the side surfaces of each chip. Namely, the side surface insulation process is not performed in the wafer state but is performed on the stacked chip module.
The disadvantages of the conventional three-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,104,820 will now be explained. First, since many processes are performed on each stacked chip module, it is impossible to adapt conventional wafer processing techniques thereto. Second, the yield of the wafer, as discussed above, is significantly reduced (about six-fold).
Third, in order to insulate the laterally realigned pads, additional process step such as chip etching and insulation polymer coating are needed; thus increasing the fabrication cost of the semiconductor chip.
In the three-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,279,991, the chips with laterally realigned pads are all stacked to form a bigger unit than a module of chips, and then the lateral surfaces of each chip are insulated. This big stacked chip unit is separated into stacked chip modules. Again, this technique requires performing many processes on the big stacked chip unit. It is impossible to directly adapt conventional wafer processing techniques thereto, thus complicating processing. In addition, an increased number of equipment must be used due to the complicated processing.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a stackable semiconductor chip, stacked semiconductor chip package and fabrication methods thereof which overcome the aforementioned problems and disadvantages of the conventional art.
It is another object of the present invention to provide an improved stackable semiconductor chip, stacked semiconductor chip package and fabrication methods thereof wherein the lateral surfaces of adjacent semiconductor chips are insulated from each other while in the wafer state.
A further object of the present invention is to provide a stackable semiconductor chip, stacked semiconductor chip package, and fabrication methods thereof which improve the yield of a wafer.
A still further object of the present invention is to provide a stackable semiconductor chip, stacked semiconductor chip package, and fabrication methods thereof which form conductive wires connected to pads of a given chip only over that given chip.
An additional object of the present invention is to provide a stacked semiconductor chip package and fabrication methods thereof which stack semiconductor chips packages having insulated lateral surfaces.
These and other objects are achieved by providing a stackable semiconductor chip package, comprising: a semiconductor chip having pads on an upper surface thereof; an adhesive formed on at least lateral surfaces of said semiconductor chip; a first insulation layer formed over said upper surface of said semiconductor chip and said adhesive, and defining a plurality of through holes which expose said pads; metal lines formed on said first insulation layer, each metal line connected to a respective one of said pads via a respective one of said through holes; and a protection layer formed on said metal lines and said first insulation layer.
These and other objects are also achieved by providing a module of stackable semiconductor chips, comprising: a plurality of stackable semiconductor chips stacked one on top of another with double-sided adhesive disposed between said stackable semiconductor chips, each one of said stackable semiconductor chips including, a semiconductor chip having pads on an upper surface thereof, an adhesive formed on at least lateral surfaces of said semiconductor chip, a first insulation layer formed over said upper surface of said semiconductor chip and said adhesive, and defining a plurality of through holes which expose said pads, metal lines formed on said first insulation layer, each metal line connected to a respective one of said pads via a respective one of said through holes, and a protection layer formed on said metal lines and said first insulation layer; and a plurality of external terminal pads formed on at least one lateral surface of said stack of stackable semiconductor chips, each one of said external terminal pads electrically connected to at least one of said metal lines in one of said stackable semiconductor chips.
These and other objects are further achieved by providing a method of manufacturing a semiconductor chip package, comprising: forming grooves between semiconductor chips of wafer, each semiconductor chip having pads formed on an upper surface thereof; filling said grooves with an adhesive; forming a first insulation layer over said first adhesive and said semiconductor chips; forming through holes in at least said first insulation layer to expose said pads on said semiconductor chips; forming metal lines on said first insulation layer, each metal line over one of said semiconductor chips being connected to a respective one of said pads on said one of said semiconductor chips; and forming a protective layer on said first insulation layer and said metal lines; removing a bottom surface of said wafer until said first adhesive is exposed; and cutting said wafer along said grooves to separate said wafer into stackable semiconductor chips.
These and other objectives are still further achieved by providing an method of manufacturing a semiconductor chip as described above which further comprises: stacking a plurality of said stackable semiconductor chips by disposing double-sided adhesive between said stackable semiconductor chips; and forming a plurality of external terminal pads on at least one lateral surface of said stack of stackable semiconductor chips, each terminal pad electrically connected to at least one of said metal lines in one of said stackable semiconductor chips.
Other objects, features, and characteristics of the present invention; methods, operation, and functions of the related elements of the structure; combination of parts; and economies of manufacture will become apparent from the following detailed description of the preferred embodiments and accompanying drawings, all of which form a part of this specification, wherein li
Kim Jin Su
Ko Hyoung Soo
Paik Kyung Wook
Birch & Stewart Kolasch & Birch, LLP
Hyundai Electronics Industries Co,. Ltd.
Williams Alexander O.
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